ARM: tegra: Add support for TK1-SOM board from Colorado Engineering

The Colorado TK1 SOM is a small form factor board similar to the
Jetson TK1.  The main differences lie in the pinmux, and in that the
PCIe controller is set to use in 4lanes+1lane, rather than 2+2.

The pinmux header here was generated from a spreadsheet provided by
Colorado Engineering using the tegra-pinmux scripts.  The spreadsheet
was converted from v09 to v11 by me.

Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7d526543848a7944550367d992715d2df42d211b..756535b75e1403abac137af459a073e1be23db56 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -57,6 +57,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
        tegra114-dalmore.dtb \
        tegra124-jetson-tk1.dtb \
        tegra124-nyan-big.dtb \
+       tegra124-cei-tk1-som.dtb \
        tegra124-venice2.dtb \
        tegra186-p2771-0000-000.dtb \
        tegra186-p2771-0000-500.dtb \

diff --git a/arch/arm/dts/tegra124-cei-tk1-som.dts b/arch/arm/dts/tegra124-cei-tk1-som.dts
new file mode 100644 (file)
index 0000000..d22c0ca
--- /dev/null
+++ b/arch/arm/dts/tegra124-cei-tk1-som.dts
@@ -0,0 +1,477 @@
+/dts-v1/;
+
+#include "tegra124.dtsi"
+
+/ {
+       model = "Colorado Engineering TK1-SOM";
+       compatible = "nvidia,cei-tk1-som", "nvidia,tegra124";
+
+       chosen {
+               stdout-path = &uartd;
+       };
+
+       aliases {
+               i2c0 = "/i2c@7000d000";
+               i2c1 = "/i2c@7000c000";
+               i2c2 = "/i2c@7000c400";
+               i2c3 = "/i2c@7000c500";
+               i2c4 = "/i2c@7000c700";
+               sdhci0 = "/sdhci@700b0600";
+               sdhci1 = "/sdhci@700b0400";
+               spi0 = "/spi@7000d400";
+               spi1 = "/spi@7000da00";
+               usb0 = "/usb@7d000000";
+               usb1 = "/usb@7d008000";
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x80000000>;
+       };
+
+       pcie-controller@01003000 {
+               status = "okay";
+
+               avddio-pex-supply = <&vdd_1v05_run>;
+               dvddio-pex-supply = <&vdd_1v05_run>;
+               avdd-pex-pll-supply = <&vdd_1v05_run>;
+               hvdd-pex-supply = <&vdd_3v3_lp0>;
+               hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
+               vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
+               avdd-pll-erefe-supply = <&avdd_1v05_run>;
+
+               pci@1,0 {
+                       status = "okay";
+                       nvidia,num-lanes = <4>;
+               };
+
+               pci@2,0 {
+                       status = "okay";
+               };
+       };
+
+       i2c@7000c000 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000c400 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000c500 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000c700 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       /* Expansion PWR_I2C_*, on-board components */
+       i2c@7000d000 {
+               status = "okay";
+               clock-frequency = <400000>;
+
+               pmic: pmic@40 {
+                       compatible = "ams,as3722";
+                       reg = <0x40>;
+                       interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+                       ams,system-power-controller;
+
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&as3722_default>;
+
+                       as3722_default: pinmux {
+                               gpio0 {
+                                       pins = "gpio0";
+                                       function = "gpio";
+                                       bias-pull-down;
+                               };
+
+                               gpio1_2_4_7 {
+                                       pins = "gpio1", "gpio2", "gpio4", "gpio7";
+                                       function = "gpio";
+                                       bias-pull-up;
+                               };
+
+                               gpio3_5_6 {
+                                       pins = "gpio3", "gpio5", "gpio6";
+                                       bias-high-impedance;
+                               };
+                       };
+
+                       regulators {
+                               vsup-sd2-supply = <&vdd_5v0_sys>;
+                               vsup-sd3-supply = <&vdd_5v0_sys>;
+                               vsup-sd4-supply = <&vdd_5v0_sys>;
+                               vsup-sd5-supply = <&vdd_5v0_sys>;
+                               vin-ldo0-supply = <&vdd_1v35_lp0>;
+                               vin-ldo1-6-supply = <&vdd_3v3_run>;
+                               vin-ldo2-5-7-supply = <&vddio_1v8>;
+                               vin-ldo3-4-supply = <&vdd_3v3_sys>;
+                               vin-ldo9-10-supply = <&vdd_5v0_sys>;
+                               vin-ldo11-supply = <&vdd_3v3_run>;
+
+                               sd0 {
+                                       regulator-name = "+VDD_CPU_AP";
+                                       regulator-min-microvolt = <700000>;
+                                       regulator-max-microvolt = <1400000>;
+                                       regulator-min-microamp = <3500000>;
+                                       regulator-max-microamp = <3500000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                                       ams,ext-control = <2>;
+                               };
+
+                               sd1 {
+                                       regulator-name = "+VDD_CORE";
+                                       regulator-min-microvolt = <700000>;
+                                       regulator-max-microvolt = <1350000>;
+                                       regulator-min-microamp = <2500000>;
+                                       regulator-max-microamp = <2500000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                                       ams,ext-control = <1>;
+                               };
+
+                               vdd_1v35_lp0: sd2 {
+                                       regulator-name = "+1.35V_LP0(sd2)";
+                                       regulator-min-microvolt = <1350000>;
+                                       regulator-max-microvolt = <1350000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               sd3 {
+                                       regulator-name = "+1.35V_LP0(sd3)";
+                                       regulator-min-microvolt = <1350000>;
+                                       regulator-max-microvolt = <1350000>;
+                                       regulator-always-on;
+                                       regulator-boot-on;
+                               };
+
+                               vdd_1v05_run: sd4 {
+                                       regulator-name = "+1.05V_RUN";
+                                       regulator-min-microvolt = <1050000>;
+                                       regulator-max-microvolt = <1050000>;
+                               };
+
+                               vddio_1v8: sd5 {
+                                       regulator-name = "+1.8V_VDDIO";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                                       regulator-boot-on;
+                                       regulator-always-on;
+                               };
+
+                               vdd_gpu: sd6 {
+                                       regulator-name = "+VDD_GPU_AP";
+                                       regulator-min-microvolt = <650000>;
+                                       regulator-max-microvolt = <1200000>;
+                                       regulator-min-microamp = <3500000>;
+                                       regulator-max-microamp = <3500000>;
+                                       regulator-boot-on;
+                                       regulator-always-on;
+                               };
+
+                               avdd_1v05_run: ldo0 {
+                                       regulator-name = "+1.05V_RUN_AVDD";
+                                       regulator-min-microvolt = <1050000>;
+                                       regulator-max-microvolt = <1050000>;
+                                       regulator-boot-on;
+                                       regulator-always-on;
+                                       ams,ext-control = <1>;
+                               };
+
+                               ldo1 {
+                                       regulator-name = "+1.8V_RUN_CAM";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                               };
+
+                               ldo2 {
+                                       regulator-name = "+1.2V_GEN_AVDD";
+                                       regulator-min-microvolt = <1200000>;
+                                       regulator-max-microvolt = <1200000>;
+                                       regulator-boot-on;
+                                       regulator-always-on;
+                               };
+
+                               ldo3 {
+                                       regulator-name = "+1.05V_LP0_VDD_RTC";
+                                       regulator-min-microvolt = <1000000>;
+                                       regulator-max-microvolt = <1000000>;
+                                       regulator-boot-on;
+                                       regulator-always-on;
+                                       ams,enable-tracking;
+                               };
+
+                               ldo4 {
+                                       regulator-name = "+2.8V_RUN_CAM";
+                                       regulator-min-microvolt = <2800000>;
+                                       regulator-max-microvolt = <2800000>;
+                               };
+
+                               ldo5 {
+                                       regulator-name = "+1.2V_RUN_CAM_FRONT";
+                                       regulator-min-microvolt = <1200000>;
+                                       regulator-max-microvolt = <1200000>;
+                               };
+
+                               vddio_sdmmc3: ldo6 {
+                                       regulator-name = "+VDDIO_SDMMC3";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <3300000>;
+                               };
+
+                               ldo7 {
+                                       regulator-name = "+1.05V_RUN_CAM_REAR";
+                                       regulator-min-microvolt = <1050000>;
+                                       regulator-max-microvolt = <1050000>;
+                               };
+
+                               ldo9 {
+                                       regulator-name = "+3.3V_RUN_TOUCH";
+                                       regulator-min-microvolt = <2800000>;
+                                       regulator-max-microvolt = <2800000>;
+                               };
+
+                               ldo10 {
+                                       regulator-name = "+2.8V_RUN_CAM_AF";
+                                       regulator-min-microvolt = <2800000>;
+                                       regulator-max-microvolt = <2800000>;
+                               };
+
+                               ldo11 {
+                                       regulator-name = "+1.8V_RUN_VPP_FUSE";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                               };
+                       };
+               };
+       };
+
+       i2c@7000d100 {
+               status = "okay";
+               clock-frequency = <400000>;
+       };
+
+       spi@7000d400 {
+               status = "okay";
+               spi-max-frequency = <25000000>;
+       };
+
+       spi@7000da00 {
+               status = "okay";
+               spi-max-frequency = <25000000>;
+       };
+
+       padctl@7009f000 {
+               pinctrl-0 = <&padctl_default>;
+               pinctrl-names = "default";
+
+               padctl_default: pinmux {
+                       usb3 {
+                               nvidia,lanes = "sata-0";
+                               nvidia,function = "usb3";
+                               nvidia,iddq = <0>;
+                       };
+
+                       pcie {
+                               nvidia,lanes = "pcie-0", "pcie-1", "pcie-2", "pcie-3",
+                                             "pcie-4";
+                               nvidia,function = "pcie";
+                               nvidia,iddq = <0>;
+                       };
+
+               };
+       };
+
+       sdhci@700b0400 {
+               status = "okay";
+               cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+               power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+               wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
+               bus-width = <4>;
+       };
+
+       sdhci@700b0600 {
+               status = "okay";
+               bus-width = <8>;
+       };
+
+       usb@7d000000 {
+               status = "okay";
+               dr_mode = "otg";
+               nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+       };
+
+       usb@7d008000 {
+               status = "okay";
+               nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+       };
+
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg = <0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
+       regulators {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               vdd_mux: regulator@0 {
+                       compatible = "regulator-fixed";
+                       reg = <0>;
+                       regulator-name = "+VDD_MUX";
+                       regulator-min-microvolt = <12000000>;
+                       regulator-max-microvolt = <12000000>;
+                       regulator-always-on;
+                       regulator-boot-on;
+               };
+
+               vdd_5v0_sys: regulator@1 {
+                       compatible = "regulator-fixed";
+                       reg = <1>;
+                       regulator-name = "+5V_SYS";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       regulator-always-on;
+                       regulator-boot-on;
+                       vin-supply = <&vdd_mux>;
+               };
+
+               vdd_3v3_sys: regulator@2 {
+                       compatible = "regulator-fixed";
+                       reg = <2>;
+                       regulator-name = "+3.3V_SYS";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       regulator-always-on;
+                       regulator-boot-on;
+                       vin-supply = <&vdd_mux>;
+               };
+
+               vdd_3v3_run: regulator@3 {
+                       compatible = "regulator-fixed";
+                       reg = <3>;
+                       regulator-name = "+3.3V_RUN";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       regulator-always-on;
+                       regulator-boot-on;
+                       gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+                       vin-supply = <&vdd_3v3_sys>;
+               };
+
+               vdd_3v3_hdmi: regulator@4 {
+                       compatible = "regulator-fixed";
+                       reg = <4>;
+                       regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       vin-supply = <&vdd_3v3_run>;
+               };
+
+               vdd_usb1_vbus: regulator@7 {
+                       compatible = "regulator-fixed";
+                       reg = <7>;
+                       regulator-name = "+USB0_VBUS_SW";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+                       gpio-open-drain;
+                       vin-supply = <&vdd_5v0_sys>;
+               };
+
+               vdd_usb3_vbus: regulator@8 {
+                       compatible = "regulator-fixed";
+                       reg = <8>;
+                       regulator-name = "+5V_USB_HS";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+                       gpio-open-drain;
+                       vin-supply = <&vdd_5v0_sys>;
+               };
+
+               vdd_3v3_lp0: regulator@10 {
+                       compatible = "regulator-fixed";
+                       reg = <10>;
+                       regulator-name = "+3.3V_LP0";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       regulator-always-on;
+                       regulator-boot-on;
+                       gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+                       vin-supply = <&vdd_3v3_sys>;
+               };
+
+               vdd_hdmi_pll: regulator@11 {
+                       compatible = "regulator-fixed";
+                       reg = <11>;
+                       regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+                       regulator-min-microvolt = <1050000>;
+                       regulator-max-microvolt = <1050000>;
+                       gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+                       vin-supply = <&vdd_1v05_run>;
+               };
+
+               vdd_5v0_hdmi: regulator@12 {
+                       compatible = "regulator-fixed";
+                       reg = <12>;
+                       regulator-name = "+5V_HDMI_CON";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+                       vin-supply = <&vdd_5v0_sys>;
+               };
+
+               /* Molex power connector */
+               vdd_5v0_sata: regulator@13 {
+                       compatible = "regulator-fixed";
+                       reg = <13>;
+                       regulator-name = "+5V_SATA";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+                       vin-supply = <&vdd_5v0_sys>;
+               };
+
+               vdd_12v0_sata: regulator@14 {
+                       compatible = "regulator-fixed";
+                       reg = <14>;
+                       regulator-name = "+12V_SATA";
+                       regulator-min-microvolt = <12000000>;
+                       regulator-max-microvolt = <12000000>;
+                       gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+                       vin-supply = <&vdd_mux>;
+               };
+       };
+};

diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig
index f3324ffaa832f8e5279f5a2e2f9db1f0f3426dd9..9e21e3099db5922d2a7f2abaa1622f6ef7a2d345 100644 (file)
--- a/arch/arm/mach-tegra/tegra124/Kconfig
+++ b/arch/arm/mach-tegra/tegra124/Kconfig
@@ -9,6 +9,17 @@ config TARGET_JETSON_TK1
        select CPU_V7_HAS_NONSEC if !SPL_BUILD
        select CPU_V7_HAS_VIRT if !SPL_BUILD
 
+config TARGET_CEI_TK1_SOM
+       bool "Colorado Engineering Inc Tegra124 TK1-som board"
+       select CPU_V7_HAS_NONSEC if !SPL_BUILD
+       select CPU_V7_HAS_VIRT if !SPL_BUILD
+       help
+         The Colorado Engineering Tegra TK1-SOM is a very compact
+         (51mmx58mm) board that is functionally almost the same as
+         the Jetson TK1.  The main differences are in which balls on
+         the SoC are assigned to which functions, and the PCIEe
+         configuration.
+
 config TARGET_NYAN_BIG
        bool "Google/NVIDIA Nyan-big Chromebook"
        help
@@ -26,6 +37,7 @@ endchoice
 config SYS_SOC
        default "tegra124"
 
+source "board/cei/cei-tk1-som/Kconfig"
 source "board/nvidia/jetson-tk1/Kconfig"
 source "board/nvidia/nyan-big/Kconfig"
 source "board/nvidia/venice2/Kconfig"

diff --git a/board/cei/cei-tk1-som/Kconfig b/board/cei/cei-tk1-som/Kconfig
new file mode 100644 (file)
index 0000000..5fcb51f
--- /dev/null
+++ b/board/cei/cei-tk1-som/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CEI_TK1_SOM
+
+config SYS_BOARD
+       default "cei-tk1-som"
+
+config SYS_VENDOR
+       default "cei"
+
+config SYS_CONFIG_NAME
+       default "cei-tk1-som"
+
+endif

diff --git a/board/cei/cei-tk1-som/MAINTAINERS b/board/cei/cei-tk1-som/MAINTAINERS
new file mode 100644 (file)
index 0000000..192e1a3
--- /dev/null
+++ b/board/cei/cei-tk1-som/MAINTAINERS
@@ -0,0 +1,6 @@
+TK1-SOM BOARD
+M:     Peter.Chubb@data61.csiro.au
+S:     Maintained
+F:     board/cei/tk1-som/
+F:     include/configs/cei-tk1-som.h
+F:     configs/cei-tk1-som_defconfig

diff --git a/board/cei/cei-tk1-som/Makefile b/board/cei/cei-tk1-som/Makefile
new file mode 100644 (file)
index 0000000..127b104
--- /dev/null
+++ b/board/cei/cei-tk1-som/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += ../../nvidia/venice2/as3722_init.o
+obj-y  += cei-tk1-som.o

diff --git a/board/cei/cei-tk1-som/cei-tk1-som.c b/board/cei/cei-tk1-som/cei-tk1-som.c
new file mode 100644 (file)
index 0000000..9ba7490
--- /dev/null
+++ b/board/cei/cei-tk1-som/cei-tk1-som.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <power/as3722.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+
+#include "pinmux-config-cei-tk1-som.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+       pinmux_clear_tristate_input_clamping();
+
+       gpio_config_table(cei_tk1_som_gpio_inits,
+                         ARRAY_SIZE(cei_tk1_som_gpio_inits));
+
+       pinmux_config_pingrp_table(cei_tk1_som_pingrps,
+                                  ARRAY_SIZE(cei_tk1_som_pingrps));
+
+       pinmux_config_drvgrp_table(cei_tk1_som_drvgrps,
+                                  ARRAY_SIZE(cei_tk1_som_drvgrps));
+
+       pinmux_config_mipipadctrlgrp_table(cei_tk1_som_mipipadctrlgrps,
+                                           ARRAY_SIZE(cei_tk1_som_mipipadctrlgrps));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+       struct udevice *pmic;
+       int err;
+
+       err = as3722_init(&pmic);
+       if (err) {
+               error("failed to initialize AS3722 PMIC: %d\n", err);
+               return err;
+       }
+
+       err = as3722_sd_enable(pmic, 4);
+       if (err < 0) {
+               error("failed to enable SD4: %d\n", err);
+               return err;
+       }
+
+       err = as3722_sd_set_voltage(pmic, 4, 0x24);
+       if (err < 0) {
+               error("failed to set SD4 voltage: %d\n", err);
+               return err;
+       }
+
+       return 0;
+}
+#endif /* PCI */

diff --git a/board/cei/cei-tk1-som/pinmux-config-cei-tk1-som.h b/board/cei/cei-tk1-som/pinmux-config-cei-tk1-som.h
new file mode 100644 (file)
index 0000000..3431bfe
--- /dev/null
+++ b/board/cei/cei-tk1-som/pinmux-config-cei-tk1-som.h
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
+ *
+ * To generate this file, use the tegra-pinmux-scripts tool available from
+ * https://github.com/NVIDIA/tegra-pinmux-scripts
+ * Run "board-to-uboot.py cei-tk1-som".
+ */
+
+#ifndef _PINMUX_CONFIG_CEI_TK1_SOM_H_
+#define _PINMUX_CONFIG_CEI_TK1_SOM_H_
+
+#define GPIO_INIT(_port, _gpio, _init)                 \
+       {                                               \
+               .gpio   = TEGRA_GPIO(_port, _gpio),     \
+               .init   = TEGRA_GPIO_INIT_##_init,      \
+       }
+
+static const struct tegra_gpio_config cei_tk1_som_gpio_inits[] = {
+       /*        port, pin, init_val */
+       GPIO_INIT(G,    0,   IN),
+       GPIO_INIT(G,    1,   IN),
+       GPIO_INIT(G,    2,   IN),
+       GPIO_INIT(G,    3,   IN),
+       GPIO_INIT(G,    4,   IN),
+       GPIO_INIT(H,    4,   IN),
+       GPIO_INIT(H,    7,   IN),
+       GPIO_INIT(I,    0,   OUT0),
+       GPIO_INIT(I,    1,   IN),
+       GPIO_INIT(I,    3,   IN),
+       GPIO_INIT(I,    6,   IN),
+       GPIO_INIT(J,    0,   IN),
+       GPIO_INIT(J,    2,   IN),
+       GPIO_INIT(K,    2,   IN),
+       GPIO_INIT(K,    6,   OUT0),
+       GPIO_INIT(N,    7,   IN),
+       GPIO_INIT(O,    1,   IN),
+       GPIO_INIT(O,    4,   IN),
+       GPIO_INIT(Q,    0,   IN),
+       GPIO_INIT(Q,    3,   IN),
+       GPIO_INIT(R,    0,   IN),
+       GPIO_INIT(R,    2,   OUT0),
+       GPIO_INIT(R,    4,   IN),
+       GPIO_INIT(R,    6,   IN),
+       GPIO_INIT(S,    2,   IN),
+       GPIO_INIT(S,    3,   IN),
+       GPIO_INIT(S,    4,   IN),
+       GPIO_INIT(S,    5,   IN),
+       GPIO_INIT(S,    6,   IN),
+       GPIO_INIT(S,    7,   IN),
+       GPIO_INIT(T,    0,   IN),
+       GPIO_INIT(T,    1,   IN),
+       GPIO_INIT(V,    0,   IN),
+       GPIO_INIT(V,    1,   IN),
+       GPIO_INIT(X,    1,   IN),
+       GPIO_INIT(X,    4,   IN),
+       GPIO_INIT(BB,   3,   OUT0),
+       GPIO_INIT(BB,   6,   OUT0),
+       GPIO_INIT(BB,   7,   OUT0),
+       GPIO_INIT(CC,   1,   IN),
+       GPIO_INIT(CC,   2,   IN),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
+       {                                                       \
+               .pingrp         = PMUX_PINGRP_##_pingrp,        \
+               .func           = PMUX_FUNC_##_mux,             \
+               .pull           = PMUX_PULL_##_pull,            \
+               .tristate       = PMUX_TRI_##_tri,              \
+               .io             = PMUX_PIN_##_io,               \
+               .od             = PMUX_PIN_OD_##_od,            \
+               .rcv_sel        = PMUX_PIN_RCV_SEL_##_rcv_sel,  \
+               .lock           = PMUX_PIN_LOCK_DEFAULT,        \
+               .ioreset        = PMUX_PIN_IO_RESET_DEFAULT,    \
+       }
+
+static const struct pmux_pingrp_config cei_tk1_som_pingrps[] = {
+       /*     pingrp,                 mux,         pull,   tri,      e_input, od,      rcv_sel */
+       PINCFG(CLK_32K_OUT_PA0,        SOC,         UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(UART3_CTS_N_PA1,        GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP2_FS_PA2,            I2S1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP2_SCLK_PA3,          I2S1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP2_DIN_PA4,           I2S1,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DAP2_DOUT_PA5,          I2S1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_CLK_PA6,         SDMMC3,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_CMD_PA7,         SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PB0,                    UARTD,       UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PB1,                    UARTD,       UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_DAT3_PB4,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_DAT2_PB5,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_DAT1_PB6,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_DAT0_PB7,        SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(UART3_RTS_N_PC0,        GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(UART2_TXD_PC2,          IRDA,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(UART2_RXD_PC3,          IRDA,        UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(GEN1_I2C_SCL_PC4,       I2C1,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(GEN1_I2C_SDA_PC5,       I2C1,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(PC7,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PG0,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PG1,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PG2,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PG3,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PG4,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PG5,                    SPI4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PG6,                    SPI4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PG7,                    SPI4,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PH0,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PH1,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PH2,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PH3,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PH4,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PH5,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PH6,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PH7,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PI0,                    DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PI1,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PI2,                    RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PI3,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PI4,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PI5,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PI6,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PI7,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PJ0,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PJ2,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(UART2_CTS_N_PJ5,        UARTB,       UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(UART2_RTS_N_PJ6,        UARTB,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PJ7,                    UARTD,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PK0,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PK1,                    RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PK2,                    DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PK3,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PK4,                    RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SPDIF_OUT_PK5,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SPDIF_IN_PK6,           DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PK7,                    UARTD,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP1_FS_PN0,            RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP1_DIN_PN1,           RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP1_DOUT_PN2,          I2S0,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP1_SCLK_PN3,          RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(USB_VBUS_EN0_PN4,       USB,         NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(USB_VBUS_EN1_PN5,       USB,         NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(HDMI_INT_PN7,           DEFAULT,     DOWN,   TRISTATE, INPUT,   DEFAULT, NORMAL),
+       PINCFG(ULPI_DATA7_PO0,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA0_PO1,         DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA1_PO2,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA2_PO3,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA3_PO4,         DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA4_PO5,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA5_PO6,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA6_PO7,         ULPI,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP3_FS_PP0,            I2S2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP3_DIN_PP1,           I2S2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP3_DOUT_PP2,          RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP3_SCLK_PP3,          RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP4_FS_PP4,            RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP4_DIN_PP5,           RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP4_DOUT_PP6,          RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP4_SCLK_PP7,          RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_COL0_PQ0,            DEFAULT,     UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_COL1_PQ1,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_COL2_PQ2,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_COL3_PQ3,            DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_COL4_PQ4,            KBC,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_COL5_PQ5,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_COL6_PQ6,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_COL7_PQ7,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW0_PR0,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW1_PR1,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW2_PR2,            DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW3_PR3,            KBC,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW4_PR4,            DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW5_PR5,            RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW6_PR6,            DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW7_PR7,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW8_PS0,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW9_PS1,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW10_PS2,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW11_PS3,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW12_PS4,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW13_PS5,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW14_PS6,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW15_PS7,           DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW16_PT0,           DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW17_PT1,           DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(GEN2_I2C_SCL_PT5,       I2C2,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(GEN2_I2C_SDA_PT6,       I2C2,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(SDMMC4_CMD_PT7,         SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PU0,                    RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PU1,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PU2,                    RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PU3,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PU4,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PU5,                    GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PU6,                    RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PV0,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PV1,                    DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_CD_N_PV2,        RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_WP_N_PV3,        SDMMC1,      DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DDC_SCL_PV4,            I2C4,        NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+       PINCFG(DDC_SDA_PV5,            I2C4,        NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+       PINCFG(GPIO_W2_AUD_PW2,        RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(GPIO_W3_AUD_PW3,        SPI6,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP_MCLK1_PW4,          EXTPERIPH1,  NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(CLK2_OUT_PW5,           RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(UART3_TXD_PW6,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(UART3_RXD_PW7,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DVFS_PWM_PX0,           CLDVFS,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(GPIO_X1_AUD_PX1,        DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DVFS_CLK_PX2,           CLDVFS,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(GPIO_X3_AUD_PX3,        RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(GPIO_X4_AUD_PX4,        DEFAULT,     NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(GPIO_X5_AUD_PX5,        RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(GPIO_X6_AUD_PX6,        GMI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(GPIO_X7_AUD_PX7,        RSVD1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(ULPI_CLK_PY0,           SPI1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(ULPI_DIR_PY1,           SPI1,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(ULPI_NXT_PY2,           SPI1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(ULPI_STP_PY3,           SPI1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_DAT3_PY4,        SDMMC1,      DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_DAT2_PY5,        SDMMC1,      DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_DAT1_PY6,        SDMMC1,      DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_DAT0_PY7,        RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_CLK_PZ0,         RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_CMD_PZ1,         SDMMC1,      DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PWR_I2C_SCL_PZ6,        I2CPWR,      NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(PWR_I2C_SDA_PZ7,        I2CPWR,      NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(SDMMC4_DAT0_PAA0,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT1_PAA1,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT2_PAA2,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT3_PAA3,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT4_PAA4,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT5_PAA5,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT6_PAA6,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT7_PAA7,       SDMMC4,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PBB0,                   VIMCLK2_ALT, NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(CAM_I2C_SCL_PBB1,       I2C3,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(CAM_I2C_SDA_PBB2,       I2C3,        NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(PBB3,                   DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PBB4,                   VGP4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PBB5,                   RSVD3,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PBB6,                   DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PBB7,                   DEFAULT,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(CAM_MCLK_PCC0,          VI_ALT3,     NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PCC1,                   DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PCC2,                   DEFAULT,     NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_CLK_PCC4,        SDMMC4,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(CLK2_REQ_PCC5,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PEX_L0_RST_N_PDD1,      PE0,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PEX_L0_CLKREQ_N_PDD2,   PE0,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PEX_WAKE_N_PDD3,        PE,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PEX_L1_RST_N_PDD5,      PE1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PEX_L1_CLKREQ_N_PDD6,   PE1,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(CLK3_OUT_PEE0,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(CLK3_REQ_PEE1,          RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP_MCLK1_REQ_PEE2,     RSVD4,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(HDMI_CEC_PEE3,          CEC,         NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,      NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,      UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DP_HPD_PFF0,            RSVD2,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(USB_VBUS_EN2_PFF1,      RSVD2,       DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PFF2,                   RSVD2,       DOWN,   TRISTATE, OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(CORE_PWR_REQ,           PWRON,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(CPU_PWR_REQ,            CPU,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PWR_INT_N,              PMI,         UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(RESET_OUT_N,            RESET_OUT_N, NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(CLK_32K_IN,             CLK,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+       PINCFG(JTAG_RTCK,              RTCK,        UP,     NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+       {                                               \
+               .drvgrp = PMUX_DRVGRP_##_drvgrp,        \
+               .slwf   = _slwf,                        \
+               .slwr   = _slwr,                        \
+               .drvup  = _drvup,                       \
+               .drvdn  = _drvdn,                       \
+               .lpmd   = PMUX_LPMD_##_lpmd,            \
+               .schmt  = PMUX_SCHMT_##_schmt,          \
+               .hsm    = PMUX_HSM_##_hsm,              \
+       }
+
+static const struct pmux_drvgrp_config cei_tk1_som_drvgrps[] = {
+};
+
+#define MIPIPADCTRLCFG(_grp, _mux) \
+       {                                                       \
+               .grp            = PMUX_MIPIPADCTRLGRP_##_grp,   \
+               .func           = PMUX_FUNC_##_mux,             \
+       }
+
+static const struct pmux_mipipadctrlgrp_config cei_tk1_som_mipipadctrlgrps[] = {
+       /*             grp,   mux */
+       MIPIPADCTRLCFG(DSI_B, DSI_B),
+};
+
+#endif /* PINMUX_CONFIG_CEI_TK1_SOM_H */

diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h
index c6b1247149e4a8ec2f1f641d8b5c7b3cf740d826..30fb132c77560ca38d89a8d094ef3db0cded799d 100644 (file)
--- a/board/nvidia/venice2/as3722_init.h
+++ b/board/nvidia/venice2/as3722_init.h
@@ -18,14 +18,14 @@
 #define AS3722_LDO6VOLTAGE_REG 0x16    /* VDD_SDMMC */
 #define AS3722_LDCONTROL_REG   0x4E
 
-#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_NYAN_BIG)
-#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
-#else
+#if defined(CONFIG_TARGET_VENICE2)
 #define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
+#else /* TK1 or Nyan-Big */
+#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
 #endif
 #define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
 
-#ifdef CONFIG_TARGET_JETSON_TK1
+#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_CEI_TK1_SOM)
 #define AS3722_SD1VOLTAGE_DATA (0x2800 | AS3722_SD1VOLTAGE_REG)
 #define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
 #endif

diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
new file mode 100644 (file)
index 0000000..0704497
--- /dev/null
+++ b/configs/cei-tk1-som_defconfig
@@ -0,0 +1,47 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_SPL_DM=y
+CONFIG_TEGRA124=y
+CONFIG_TARGET_CEI_TK1_SOM=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Tegra124 (TK1-SOM) # "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_RTL8169=y
+CONFIG_PCI_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA114_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
+CONFIG_USE_PRIVATE_LIBGCC=y

diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h
new file mode 100644 (file)
index 0000000..74fc377
--- /dev/null
+++ b/include/configs/cei-tk1-som.h
@@ -0,0 +1,73 @@
+/*
+ * (c) Copyright 2016, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ *
+ * Based on jetson-tk1.h which is:
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+/* enable PMIC */
+#define CONFIG_AS3722_POWER
+
+#include "tegra124-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING      "CEI tk1-som"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTD_BASE
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET              (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define CONFIG_SYS_MMC_ENV_PART                2
+
+/* SPI */
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED                24000000
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* PCI host support */
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_CMD_PCI
+
+/* General networking support */
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#define CONFIG_ARMV7_PSCI                      1
+#define CONFIG_ARMV7_PSCI_NR_CPUS              4
+/* Reserve top 1M for secure RAM */
+#define CONFIG_ARMV7_SECURE_BASE               0xfff00000
+#define CONFIG_ARMV7_SECURE_RESERVE_SIZE       0x00100000
+
+#endif /* __CONFIG_H */