arm: Allow skipping of low-level init with I-cache on

At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling
lowlevel_init(). This means that the instruction cache is not enabled and
the board runs very slowly.

What is really needed in many cases is to skip the call to lowlevel_init()
but still perform CP15 init. Add an option to handle this.

Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

diff --git a/README b/README
index 1d0b946977b22cc9a746515d4a9779b68b6bd64b..03bed180591a7a0cafd003f53b889991c183741e 100644 (file)
--- a/README
+++ b/README
@@ -4824,6 +4824,11 @@ Low Level (hardware related) configuration options:
                other boot loader or by a debugger which performs
                these initializations itself.
 
+- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+               [ARM926EJ-S only] This allows just the call to lowlevel_init()
+               to be skipped. The normal CPU15 init (such as enabling the
+               instruction cache) is still performed.
+
 - CONFIG_SPL_BUILD
                Modifies the behaviour of start.S when compiling a loader
                that is executed before the actual U-Boot. E.g. when

diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 3ebdfddc8098a4de195166de4f30c43fdba1f07b..2f8fd6acc20e52b1e18d5049a1db78e9f09bc425 100644 (file)
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -82,6 +82,7 @@ cpu_init_crit:
        orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
        mcr     p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        /*
         * Jump to board specific initialization... The Mask ROM will have already initialized
         * basic memory.  Go here to bump up clock rate and handle wake up conditions.
@@ -89,5 +90,6 @@ cpu_init_crit:
        mov     ip, lr          /* persevere link reg across call */
        bl      lowlevel_init   /* go setup pll,mux,memory */
        mov     lr, ip          /* restore link */
+#endif
        mov     pc, lr          /* back to my caller */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */

diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index 69cabebed91edbba882b5b7821f22aaaa3969bcc..3ada6d026fa9d37036a0bf0978e4f0c22930d9de 100644 (file)
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -135,6 +135,7 @@ cpu_init_crit:
        orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
        mcr     p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        /*
         * before relocating, we have to setup RAM timing
         * because memory timing is board-dependend, you will
@@ -143,7 +144,7 @@ cpu_init_crit:
        mov     ip, lr
 
        bl      lowlevel_init
-
        mov     lr, ip
+#endif
        mov     pc, lr
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */

diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index f05113da9df21ff5a28ebc644fc83bf5399f8606..959d1ed86d8af82c62a1f497aa90c50d3f109318 100644 (file)
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -101,11 +101,13 @@ flush_dcache:
 #endif
        mcr     p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        /*
         * Go setup Memory and board specific bits prior to relocation.
         */
        mov     ip, lr          /* perserve link reg across call */
        bl      lowlevel_init   /* go setup pll,mux,memory */
        mov     lr, ip          /* restore link */
+#endif
        mov     pc, lr          /* back to my caller */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */

diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S
index 214cd8cbd9070f36feaa046bcd56f163fe245ae7..51053c32dc11dd54aa2c9c21be917fc1c2b57028 100644 (file)
--- a/arch/arm/cpu/arm946es/start.S
+++ b/arch/arm/cpu/arm946es/start.S
@@ -90,11 +90,13 @@ cpu_init_crit:
        orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
        mcr     p15, 0, r0, c1, c0, 0
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        /*
         * Go setup Memory and board specific bits prior to relocation.
         */
        mov     ip, lr          /* perserve link reg across call */
        bl      lowlevel_init   /* go setup memory */
        mov     lr, ip          /* restore link */
+#endif
        mov     pc, lr          /* back to my caller */
 #endif

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index b18094447b0601e8a7ff539c0b286c693c66d5da..691e5d3fe165c79af45826e24cda182560333e67 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -66,7 +66,9 @@ save_boot_params_ret:
        /* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
        bl      cpu_init_cp15
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        bl      cpu_init_crit
+#endif
 #endif
 
        bl      _main
@@ -250,7 +252,8 @@ skip_errata_621766:
        mov     pc, r5                  @ back to my caller
 ENDPROC(cpu_init_cp15)
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+       !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
 /*************************************************************************
  *
  * CPU_init_critical registers

diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
index 408b70dbc1fe2f336173c9933120b4d9a1be560b..f5318c90d123f8a5c66d6f297f32f4d88323ad3a 100644 (file)
--- a/arch/arm/cpu/sa1100/start.S
+++ b/arch/arm/cpu/sa1100/start.S
@@ -96,6 +96,7 @@ cpu_init_crit:
        ldr     r1, cpuspeed
        str     r1, [r0, #PPCR]
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
        /*
         * before relocating, we have to setup RAM timing
         * because memory timing is board-dependend, you will
@@ -104,6 +105,7 @@ cpu_init_crit:
        mov     ip,     lr
        bl      lowlevel_init
        mov     lr,     ip
+#endif
 
        /*
         * disable MMU stuff and enable I-cache