mtd: spi-nor-core: Do not make invalid quad enable fatal

The Micron MT35XU512ABA flash does not support the quad enable bit. But
instead of programming the Quad Enable Require field to 000b ("Device
does not have a QE bit"), it is programmed to 111b ("Reserved").

While this is technically incorrect, it is not reason enough to abort
BFPT parsing. Instead, continue BFPT parsing assuming there is no quad
enable bit present.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index cdb464813bb462794af4f3b3a6b380d6a41fd057..b5b1ac8b5b11747f257e33e948acfabf324641cb 100644 (file)
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -2100,7 +2100,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
                break;
 #endif
        default:
-               return -EINVAL;
+               dev_dbg(nor->dev, "BFPT QER reserved value used\n");
+               break;
        }
 
        /* Stop here if JESD216 rev B. */