pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS

If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added
as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale
with the number of DRAM banks, otherwise we will end up with too little
space in the hose->regions array to store all system memory regions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/include/pci.h b/include/pci.h
index 5fb212cab1a9eada9b0bc9ca5b9fdd2ad1ca0ad3..9668503f0930ba5618dfd128a12d0dabcccdc502 100644 (file)
--- a/include/pci.h
+++ b/include/pci.h
@@ -545,7 +545,11 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
                                      struct pci_config_table *);
 
-#define MAX_PCI_REGIONS                7
+#ifdef CONFIG_NR_DRAM_BANKS
+#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7)
+#else
+#define MAX_PCI_REGIONS 7
+#endif
 
 #define INDIRECT_TYPE_NO_PCIE_LINK     1