arch/riscv: add semihosting support for RISC-V

We add RISC-V semihosting based serial console for JTAG based early
debugging.

The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h
index e8a94fcb1feaf69f965ee9841f8fb65748e3ae1e..2898a770ee27c1ccd050eb6d134b2a435a484af8 100644 (file)
--- a/arch/riscv/include/asm/spl.h
+++ b/arch/riscv/include/asm/spl.h
@@ -25,6 +25,7 @@ enum {
        BOOT_DEVICE_DFU,
        BOOT_DEVICE_XIP,
        BOOT_DEVICE_BOOTROM,
+       BOOT_DEVICE_SMH,
        BOOT_DEVICE_NONE
 };
 

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index d6a8ae97284ee4e0ae5a9afbe8c96e6204ad5a90..e5a81ba7223edb785ac986363b362b04740fc450 100644 (file)
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -42,3 +42,5 @@ extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
 obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
 obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o
 obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
+
+obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o

diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 100be2e9662e480c11e5c68c8d21851feb251edb..e966afa7e3e3647a66aed9ca82f817fdd4a03322 100644 (file)
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -9,6 +9,7 @@
  * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
  */
 
+#include <linux/compat.h>
 #include <common.h>
 #include <efi_loader.h>
 #include <hang.h>
@@ -17,6 +18,7 @@
 #include <asm/ptrace.h>
 #include <asm/system.h>
 #include <asm/encoding.h>
+#include <semihosting.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -149,6 +151,29 @@ ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs)
        /* An UEFI application may have changed gd. Restore U-Boot's gd. */
        efi_restore_gd();
 
+       if (cause == CAUSE_BREAKPOINT &&
+           CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)) {
+               ulong pre_addr = epc - 4, post_addr = epc + 4;
+
+               /* Check for prior and post addresses to be in same page. */
+               if ((pre_addr & ~(PAGE_SIZE - 1)) ==
+                       (post_addr & ~(PAGE_SIZE - 1))) {
+                       u32 pre = *(u32 *)pre_addr;
+                       u32 post = *(u32 *)post_addr;
+
+                       /* Check for semihosting, i.e.:
+                        * slli    zero,zero,0x1f
+                        * ebreak
+                        * srai    zero,zero,0x7
+                        */
+                       if (pre == 0x01f01013 && post == 0x40705013) {
+                               disable_semihosting();
+                               epc += 4;
+                               return epc;
+                       }
+               }
+       }
+
        is_irq = (cause & MCAUSE_INT);
        irq = (cause & ~MCAUSE_INT);
 

diff --git a/arch/riscv/lib/semihosting.c b/arch/riscv/lib/semihosting.c
new file mode 100644 (file)
index 0000000..d6593b0
--- /dev/null
+++ b/arch/riscv/lib/semihosting.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Ventana Micro Systems Inc.
+ */
+
+#include <common.h>
+
+long smh_trap(int sysnum, void *addr)
+{
+       register int ret asm ("a0") = sysnum;
+       register void *param0 asm ("a1") = addr;
+
+       asm volatile (".align 4\n"
+               ".option push\n"
+               ".option norvc\n"
+
+               "slli zero, zero, 0x1f\n"
+               "ebreak\n"
+               "srai zero, zero, 7\n"
+               ".option pop\n"
+               : "+r" (ret) : "r" (param0) : "memory");
+
+       return ret;
+}

diff --git a/lib/Kconfig b/lib/Kconfig
index b8833e018371dd3af833608c0b15cb619e114496..3c5a4ab38612dd79a7eb4cfeb6b86e43b7fa0ac4 100644 (file)
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -73,7 +73,7 @@ config LIB_UUID
 
 config SEMIHOSTING
        bool "Support semihosting"
-       depends on ARM
+       depends on ARM || RISCV
        help
          Semihosting is a method for a target to communicate with a host
          debugger. It uses special instructions which the debugger will trap
@@ -86,7 +86,7 @@ config SEMIHOSTING
 
 config SEMIHOSTING_FALLBACK
        bool "Recover gracefully when semihosting fails"
-       depends on SEMIHOSTING && ARM64
+       depends on SEMIHOSTING && (ARM64 || RISCV)
        default y
        help
          Normally, if U-Boot makes a semihosting call and no debugger is
@@ -96,7 +96,7 @@ config SEMIHOSTING_FALLBACK
 
 config SPL_SEMIHOSTING
        bool "Support semihosting in SPL"
-       depends on SPL && ARM
+       depends on SPL && (ARM || RISCV)
        help
          Semihosting is a method for a target to communicate with a host
          debugger. It uses special instructions which the debugger will trap
@@ -109,8 +109,8 @@ config SPL_SEMIHOSTING
 
 config SPL_SEMIHOSTING_FALLBACK
        bool "Recover gracefully when semihosting fails in SPL"
-       depends on SPL_SEMIHOSTING && ARM64
-       select ARMV8_SPL_EXCEPTION_VECTORS
+       depends on SPL_SEMIHOSTING && (ARM64 || RISCV)
+       select ARMV8_SPL_EXCEPTION_VECTORS if ARM64
        default y
        help
          Normally, if U-Boot makes a semihosting call and no debugger is