Add architecture-related code for dm fec support.
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
if (setclear) {
/* Enable Ethernet pins */
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
- struct fec_info_s *info = (struct fec_info_s *) dev->priv;
gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+ u32 fec0_base;
+
+ if (fec_get_base_addr(0, &fec0_base))
+ return -1;
if (setclear) {
/* Enable Ethernet pins */
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ if (info->iobase == fec0_base) {
setbits_be16(&gpio->par_feci2c, 0x0f00);
setbits_8(&gpio->par_fec0hl, 0xc0);
} else {
setbits_8(&gpio->par_fec1hl, 0xc0);
}
} else {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ if (info->iobase == fec0_base) {
clrbits_be16(&gpio->par_feci2c, 0x0f00);
clrbits_8(&gpio->par_fec0hl, 0xc0);
} else {
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
* create a board-specific function called:
* int board_eth_init(bd_t *bis)
*/
-
int cpu_eth_init(bd_t *bis)
{
return mcffec_initialize(bis);
#include <asm/immap.h>
#include <asm/io.h>
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_MCFFEC)
#include <config.h>
#include <net.h>
#include <asm/fec.h>
int cpu_init_r(void)
{
#ifdef CONFIG_MCFFEC
+ u32 fec_mii_base0, fec_mii_base1;
ccm_t *ccm = (ccm_t *) MMAP_CCM;
#endif
#ifdef CONFIG_MCFRTC
#endif
#ifdef CONFIG_MCFFEC
- if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
+ fec_get_mii_base(0, &fec_mii_base0);
+ fec_get_mii_base(1, &fec_mii_base1);
+
+ if (fec_mii_base0 != fec_mii_base1)
setbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
else
clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+ u32 fec0_base;
+
+ if (fec_get_base_addr(0, &fec0_base))
+ return -1;
if (setclear) {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ if (info->iobase == fec0_base) {
setbits_8(&gpio->par_fec,
GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
setbits_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1);
}
} else {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ if (info->iobase == fec0_base) {
clrbits_8(&gpio->par_fec,
GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK);
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-#ifdef CONFIG_MCF5445x
- struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+ u32 fec0_base;
+
+ if (fec_get_base_addr(0, &fec0_base))
+ return -1;
+#ifdef CONFIG_MCF5445x
if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+ if (info->iobase == fec0_base)
setbits_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC0_MDC0 |
GPIO_PAR_FECI2C_MDIO0_MDIO0);
GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
#endif
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+ if (info->iobase == fec0_base)
setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
else
setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
clrbits_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ if (info->iobase == fec0_base) {
#ifdef CONFIG_SYS_FEC_FULL_MII
setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
#else
return 0;
}
#endif
-
#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
+#include <asm/fec.h>
#include <asm/fsl_mcdmafec.h>
#endif
}
#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
+int fecpin_setclear(fec_info_t *info, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
+ u32 fec0_base;
+
+ if (fec_get_base_addr(0, &fec0_base))
+ return -1;
if (setclear) {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+ if (info->iobase == fec0_base)
setbits_be16(&gpio->par_feci2cirq, 0xf000);
else
setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
} else {
- if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+ if (info->iobase == fec0_base)
clrbits_be16(&gpio->par_feci2cirq, 0xf000);
else
clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
int phyname_init;
cbd_t *rxbd; /* Rx BD */
cbd_t *txbd; /* Tx BD */
- uint rxIdx;
- uint txIdx;
+ uint rx_idx;
+ uint tx_idx;
char *txbuf;
int initialized;
- struct fec_info_s *next;
+ int to_loop;
+ struct mii_dev *bus;
};
#ifdef CONFIG_MCFFEC
#define FEC_RESET_DELAY 100
#define FEC_RX_TOUT 100
-int fecpin_setclear(struct eth_device *dev, int setclear);
+#ifdef CONFIG_MCF547x_8x
+typedef struct fec_info_dma fec_info_t;
+#define FEC_T fecdma_t
+#else
+typedef struct fec_info_s fec_info_t;
+#define FEC_T fec_t
+#endif
+
+int fecpin_setclear(fec_info_t *info, int setclear);
+int mii_discover_phy(fec_info_t *info);
+int fec_get_base_addr(int fec_idx, u32 *fec_iobase);
+int fec_get_mii_base(int fec_idx, u32 *mii_base);
#ifdef CONFIG_SYS_DISCOVER_PHY
void __mii_init(void);
uint mii_send(uint mii_cmd);
-int mii_discover_phy(struct eth_device *dev);
int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 value);
int phyname_init;
cbd_t *rxbd; /* Rx BD */
cbd_t *txbd; /* Tx BD */
- uint rxIdx;
- uint txIdx;
+ uint rx_idx;
+ uint tx_idx;
char *txbuf;
int initialized;
struct fec_info_dma *next;
-
- u16 rxTask; /* DMA receive Task Number */
- u16 txTask; /* DMA Transmit Task Number */
- u16 rxPri; /* DMA Receive Priority */
- u16 txPri; /* DMA Transmit Priority */
- u16 rxInit; /* DMA Receive Initiator */
- u16 txInit; /* DMA Transmit Initiator */
- u16 usedTbdIdx; /* next transmit BD to clean */
- u16 cleanTbdNum; /* the number of available transmit BDs */
+ u16 rx_task; /* DMA receive Task Number */
+ u16 tx_task; /* DMA Transmit Task Number */
+ u16 rx_pri; /* DMA Receive Priority */
+ u16 tx_pri; /* DMA Transmit Priority */
+ u16 rx_init; /* DMA Receive Initiator */
+ u16 tx_init; /* DMA Transmit Initiator */
+ u16 used_tbd_idx; /* next transmit BD to clean */
+ u16 clean_tbd_num; /* the number of available transmit BDs */
+ int to_loop;
+ struct mii_dev *bus;
};
/* Bit definitions and macros for IEVENT */
obj-y += interrupts.o
obj-y += time.o
obj-y += traps.o
+obj-y += fec.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
+ */
+
+#include <common.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_MCFFEC) || defined(CONFIG_FSLDMAFEC)
+static int fec_get_node(int fec_idx)
+{
+ char fec_alias[5] = {"fec"};
+ const char *path;
+ int node;
+
+ if (fec_idx > 1) {
+ puts("Invalid MII base index");
+ return -ENOENT;
+ }
+
+ fec_alias[3] = fec_idx + '0';
+
+ path = fdt_get_alias(gd->fdt_blob, fec_alias);
+ if (!path) {
+ puts("Invalid MII path");
+ return -ENOENT;
+ }
+
+ node = fdt_path_offset(gd->fdt_blob, path);
+ if (node < 0)
+ return -ENOENT;
+
+ return node;
+}
+
+int fec_get_fdt_prop(int fec_idx, const char *prop, u32 *value)
+{
+ int node;
+ const u32 *val;
+
+ node = fec_get_node(fec_idx);
+ if (node < 0)
+ return node;
+
+ val = fdt_getprop(gd->fdt_blob, node, prop, NULL);
+ if (!val)
+ return -ENOENT;
+
+ *value = fdt32_to_cpu(*val);
+
+ return 0;
+}
+
+int fec_get_base_addr(int fec_idx, u32 *fec_iobase)
+{
+ int node;
+ fdt_size_t size;
+ fdt_addr_t addr;
+
+ node = fec_get_node(fec_idx);
+ if (node < 0)
+ return node;
+
+ addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
+
+ *fec_iobase = (u32)addr;
+
+ return 0;
+}
+
+int fec_get_mii_base(int fec_idx, u32 *mii_base)
+{
+ return fec_get_fdt_prop(fec_idx, "mii-base", mii_base);
+}
+
+#endif //CONFIG_MCFFEC || CONFIG_FSLDMAFEC