MIPS: Move cache sizes to Kconfig

Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a9294527df7a63399f1e2ace8fbf5adf50368434..a79224e525ed34bae477b8cecd709aa9588a5eb2 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -246,6 +246,34 @@ config SWAP_IO_SPACE
 config SYS_MIPS_CACHE_INIT_RAM_LOAD
        bool
 
+config SYS_DCACHE_SIZE
+       int
+       default 0
+       help
+         The total size of the L1 Dcache, if known at compile time.
+
+config SYS_ICACHE_SIZE
+       int
+       default 0
+       help
+         The total size of the L1 ICache, if known at compile time.
+
+config SYS_CACHELINE_SIZE
+       int
+       default 0
+       help
+         The size of L1 cache lines, if known at compile time.
+
+config SYS_CACHE_SIZE_AUTO
+       def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
+               SYS_CACHELINE_SIZE = 0
+       help
+         Select this (or let it be auto-selected by not defining any cache
+         sizes) in order to allow U-Boot to automatically detect the sizes
+         of caches at runtime. This has a small cost in code size & runtime
+         so if you know the cache configuration for your system at compile
+         time it would be beneficial to configure it.
+
 config MIPS_L1_CACHE_SHIFT_4
        bool
 

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 7482005b6796304f108317284d6427024c7c9613..fbaafee8cdeaac121e728ea886311ad409c1f1ef 100644 (file)
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -9,7 +9,7 @@
 #include <asm/cacheops.h>
 #include <asm/mipsregs.h>
 
-#ifdef CONFIG_SYS_CACHELINE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 
 static inline unsigned long icache_line_size(void)
 {

diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 08b7c3af5254b80b08e2ecd04a815795e9ca458a..4bb9a17e749add16f0d709fea614a6bb27fe88eb 100644 (file)
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -99,14 +99,14 @@
  *
  */
 LEAF(mips_cache_reset)
-#ifdef CONFIG_SYS_ICACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
        li      t2, CONFIG_SYS_ICACHE_SIZE
        li      t8, CONFIG_SYS_CACHELINE_SIZE
 #else
        l1_info t2, t8, MIPS_CONF1_IA_SHF
 #endif
 
-#ifdef CONFIG_SYS_DCACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
        li      t3, CONFIG_SYS_DCACHE_SIZE
        li      t9, CONFIG_SYS_CACHELINE_SIZE
 #else
@@ -116,7 +116,7 @@ LEAF(mips_cache_reset)
 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
 
        /* Determine the largest L1 cache size */
-#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
        li      v0, CONFIG_SYS_ICACHE_SIZE
 #else

diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
index 342ec59cb7396677b3bde3982a35a861749d6d4e..1715a2897553db3ddb4a5632d1bcf92d95f7ad4a 100644 (file)
--- a/board/dbau1x00/Kconfig
+++ b/board/dbau1x00/Kconfig
@@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
        default 0xbfc00000
 
+config SYS_DCACHE_SIZE
+       default 16384
+
+config SYS_ICACHE_SIZE
+       default 16384
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 menu "dbau1x00 board options"
 
 choice

diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index 535a77b2a32ecdc8610a6c9023767614d31e63aa..5bb6f03f30f178c3e5a3bb9cd214cc28dddefd53 100644 (file)
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
        default 0x87000000
 
+config SYS_DCACHE_SIZE
+       default 16384
+
+config SYS_ICACHE_SIZE
+       default 16384
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 menu "vct board options"
 
 choice

diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
index 236a4108bfc044673e115fde64967b9dcc3148a2..27b2ef000b0937a6e5a1e514b2683ff4c1aaaf9f 100644 (file)
--- a/board/pb1x00/Kconfig
+++ b/board/pb1x00/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
        default 0x83800000
 
+config SYS_DCACHE_SIZE
+       default 16384
+
+config SYS_ICACHE_SIZE
+       default 16384
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 endif

diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
index c3ecc8f62ff6e3717e02c1186af1114fb73a4f10..f28ea1cd44f4041b1ec16e6524e658e2955a943d 100644 (file)
--- a/board/qca/ap121/Kconfig
+++ b/board/qca/ap121/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
        default 0x9f000000
 
+config SYS_DCACHE_SIZE
+       default 32768
+
+config SYS_ICACHE_SIZE
+       default 65536
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 endif

diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
index 5ea5d6fbb02455b818d17b390b68d190ad7794f9..ff02236d5d834650807f564a79d823a3b43692bd 100644 (file)
--- a/board/qca/ap143/Kconfig
+++ b/board/qca/ap143/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
        default 0x9f000000
 
+config SYS_DCACHE_SIZE
+       default 32768
+
+config SYS_ICACHE_SIZE
+       default 65536
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 endif

diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
index 3de1f44a3da4585b4a94ca1424f29a915343799c..66957e7a57ac005db1f963eb6a99079a83801945 100644 (file)
--- a/board/qemu-mips/Kconfig
+++ b/board/qemu-mips/Kconfig
@@ -11,4 +11,13 @@ config SYS_TEXT_BASE
        default 0xbfc00000 if 32BIT
        default 0xffffffffbfc00000 if 64BIT
 
+config SYS_DCACHE_SIZE
+       default 16384
+
+config SYS_ICACHE_SIZE
+       default 16384
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 endif

diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
index 65785bdb9c752a09182b2a0beadb98ef14bfb9ea..ded7f9b1798dfdd2bae10a13dfc4189b10fda016 100644 (file)
--- a/board/tplink/wdr4300/Kconfig
+++ b/board/tplink/wdr4300/Kconfig
@@ -15,4 +15,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
        default 0xa1000000
 
+config SYS_DCACHE_SIZE
+       default 32768
+
+config SYS_ICACHE_SIZE
+       default 65536
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 endif

diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 6f69f31503c26aed745fdc13d2b40cbe5beeb573..f069d501302c1242f5dff8d02a9624b4bcf3d803 100644 (file)
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -15,11 +15,6 @@
 #define CONFIG_SYS_MHZ                  200
 #define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE          0x8000
-#define CONFIG_SYS_ICACHE_SIZE          0x10000
-#define CONFIG_SYS_CACHELINE_SIZE       32
-
 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN           0x40000

diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index f907c02af922667224d2479b56a30b42a5af1d5c..e45f743936da4fa25a63aa41497ef92c68f36294 100644 (file)
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -15,11 +15,6 @@
 #define CONFIG_SYS_MHZ                  325
 #define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE          0x8000
-#define CONFIG_SYS_ICACHE_SIZE          0x10000
-#define CONFIG_SYS_CACHELINE_SIZE       32
-
 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN           0x40000

diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 68d9e36b19cc0b033cedda7f03559f20c0b9b764..68ff02509b5e039eccd6c6aaa2002f771f6723e6 100644 (file)
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -202,11 +202,4 @@
 #define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 #endif /* CONFIG_DBAU1550 */
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE         16384
-#define CONFIG_SYS_ICACHE_SIZE         16384
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #endif /* __CONFIG_H */

diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index 869768add054268d542d18f64802557ae3152247..b907419a5987fcbb1fa834aa98f13e6878c3a181 100644 (file)
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -144,12 +144,6 @@
 #define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 
 #endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE         16384
-#define CONFIG_SYS_ICACHE_SIZE         16384
-#define CONFIG_SYS_CACHELINE_SIZE      32
 
 /*
  * BOOTP options

diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 246ee0173a74755d4b45abaa98bdc0df00eb22de..f58fc4c377956cbbf70a47a622988f3337302ba9 100644 (file)
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -132,11 +132,4 @@
 
 #define CONFIG_LZMA
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE         16384
-#define CONFIG_SYS_ICACHE_SIZE         16384
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #endif /* __CONFIG_H */

diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 60a3a71fbdc5e335a0d3f62b4a42cc1d0438acd9..2190d162007e99e3cc9a60a77fef3dedfd751e07 100644 (file)
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -132,11 +132,4 @@
 
 #define CONFIG_LZMA
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE         16384
-#define CONFIG_SYS_ICACHE_SIZE         16384
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #endif /* __CONFIG_H */

diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 09a69fec09d88902bb66f48962179bb316e7c8d4..6273711b1d074d5a6fdd570723bb9d29e530086e 100644 (file)
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -15,11 +15,6 @@
 #define CONFIG_SYS_MHZ                 280
 #define CONFIG_SYS_MIPS_TIMER_FREQ     (CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE         0x8000
-#define CONFIG_SYS_ICACHE_SIZE         0x10000
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN          0x40000

diff --git a/include/configs/vct.h b/include/configs/vct.h
index 68eb0893948faee401614d2bf3f54b6e73edc381..cc5e3546b08cc330abc1d5c2e75dd3a8cebf466a 100644 (file)
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -203,13 +203,6 @@
 #define        CONFIG_ENV_SIZE                 (128 << 10)     /* erase size */
 #endif /* CONFIG_VCT_ONENAND */
 
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE         16384
-#define CONFIG_SYS_ICACHE_SIZE         16384
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 /*
  * I2C/EEPROM
  */