net: sun8i_emac: Use consistent clock bitfield definitions

While the R40 uses a different register for EMAC clock configuration
than other chips, the register has a very similar layout. Reuse the
existing bitfield definitions in this file, since they match.

This allows the driver to compile on the H6 platform, where the
CCM_GMAC_CTRL definitions are not present.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 99e24c634828b6966c6ae06e19d5c338865788a7..edbec9f3a8bdf96941ba9cd0a82c26c1c89d8247 100644 (file)
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -300,9 +300,9 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
        if (priv->variant == R40_GMAC) {
                /* Select RGMII for R40 */
                reg = readl(priv->sysctl_reg + 0x164);
-               reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
-                      CCM_GMAC_CTRL_GPIT_RGMII |
-                      CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
+               reg |= SC_ETCS_INT_GMII |
+                      SC_EPIT |
+                      (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
 
                writel(reg, priv->sysctl_reg + 0x164);
                return 0;