Armada100: Enable Ethernet support for GplugD

This patch enables ethernet support for Marvell GplugD board. Network
related commands works.

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>

diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
index 9b9ed165e035f38f4449a6a374e032e0af353ef3..c449d4e63997d73a3e7cbfc82fdd4d1ac38e142c 100644 (file)
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -41,6 +41,10 @@
 /* Functional Clock Selection Mask */
 #define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
 
+/* Fast Ethernet Controller Clock register definition */
+#define FE_CLK_RST             0x1
+#define FE_CLK_ENA             0x8
+
 /* Register Base Addresses */
 #define ARMD1_DRAM_BASE                0xB0000000
 #define ARMD1_FEC_BASE         0xC0800000
@@ -84,6 +88,59 @@ struct armd1mpmu_registers {
        u32 arsr;       /*0x1028*/
 };
 
+/*
+ * Application Subsystem Power Management
+ * Refer Datasheet Appendix A.9
+ */
+struct armd1apmu_registers {
+       u32 pcr;                /* 0x000 */
+       u32 ccr;                /* 0x004 */
+       u32 pad1;
+       u32 ccsr;               /* 0x00C */
+       u32 fc_timer;           /* 0x010 */
+       u32 pad2;
+       u32 ideal_cfg;          /* 0x018 */
+       u8 pad3[0x04C - 0x018 - 4];
+       u32 lcdcrc;             /* 0x04C */
+       u32 cciccrc;            /* 0x050 */
+       u32 sd1crc;             /* 0x054 */
+       u32 sd2crc;             /* 0x058 */
+       u32 usbcrc;             /* 0x05C */
+       u32 nfccrc;             /* 0x060 */
+       u32 dmacrc;             /* 0x064 */
+       u32 pad4;
+       u32 buscrc;             /* 0x06C */
+       u8 pad5[0x07C - 0x06C - 4];
+       u32 wake_clr;           /* 0x07C */
+       u8 pad6[0x090 - 0x07C - 4];
+       u32 core_status;        /* 0x090 */
+       u32 rfsc;               /* 0x094 */
+       u32 imr;                /* 0x098 */
+       u32 irwc;               /* 0x09C */
+       u32 isr;                /* 0x0A0 */
+       u8 pad7[0x0B0 - 0x0A0 - 4];
+       u32 mhst;               /* 0x0B0 */
+       u32 msr;                /* 0x0B4 */
+       u8 pad8[0x0C0 - 0x0B4 - 4];
+       u32 msst;               /* 0x0C0 */
+       u32 pllss;              /* 0x0C4 */
+       u32 smb;                /* 0x0C8 */
+       u32 gccrc;              /* 0x0CC */
+       u8 pad9[0x0D4 - 0x0CC - 4];
+       u32 smccrc;             /* 0x0D4 */
+       u32 pad10;
+       u32 xdcrc;              /* 0x0DC */
+       u32 sd3crc;             /* 0x0E0 */
+       u32 sd4crc;             /* 0x0E4 */
+       u8 pad11[0x0F0 - 0x0E4 - 4];
+       u32 cfcrc;              /* 0x0F0 */
+       u32 mspcrc;             /* 0x0F4 */
+       u32 cmucrc;             /* 0x0F8 */
+       u32 fecrc;              /* 0x0FC */
+       u32 pciecrc;            /* 0x100 */
+       u32 epdcrc;             /* 0x104 */
+};
+
 /*
  * APB1 Clock Reset/Control Registers
  * Refer Datasheet Appendix A.10

diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h
index d6e0494b7ed1cbc4e38bc81a140c03b1f861de70..da76b58405e1274767075e7a83dbd5c6df6947f1 100644 (file)
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -64,6 +64,25 @@
 #define MFP105_CI2C_SDA                (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
 #define MFP106_CI2C_SCL                (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
 
+/* Fast Ethernet */
+#define MFP086_ETH_TXCLK       (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP087_ETH_TXEN                (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP088_ETH_TXDQ3       (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP089_ETH_TXDQ2       (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP090_ETH_TXDQ1       (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP091_ETH_TXDQ0       (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP092_ETH_CRS         (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP093_ETH_COL         (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP094_ETH_RXCLK       (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP095_ETH_RXER                (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP096_ETH_RXDQ3       (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP097_ETH_RXDQ2       (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP098_ETH_RXDQ1       (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP099_ETH_RXDQ0       (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP100_ETH_MDC         (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP101_ETH_MDIO                (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP103_ETH_RXDV                (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+
 /* More macros can be defined here... */
 
 #define MFP_PIN_MAX    117

diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index dc7d89d82d0cc45e5f8c16fc2c6fe804d46135e8..8560b3f109c39ec452b9069475483307cd4869a3 100644 (file)
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -33,6 +33,11 @@
 #include <asm/arch/mfp.h>
 #include <asm/arch/armada100.h>
 
+#ifdef CONFIG_ARMADA100_FEC
+#include <net.h>
+#include <netdev.h>
+#endif /* CONFIG_ARMADA100_FEC */
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_early_init_f(void)
@@ -45,6 +50,26 @@ int board_early_init_f(void)
                /* Enable Console on UART3 */
                MFPO8_UART3_TXD,
                MFPO9_UART3_RXD,
+
+               /* Ethernet PHY Interface */
+               MFP086_ETH_TXCLK,
+               MFP087_ETH_TXEN,
+               MFP088_ETH_TXDQ3,
+               MFP089_ETH_TXDQ2,
+               MFP090_ETH_TXDQ1,
+               MFP091_ETH_TXDQ0,
+               MFP092_ETH_CRS,
+               MFP093_ETH_COL,
+               MFP094_ETH_RXCLK,
+               MFP095_ETH_RXER,
+               MFP096_ETH_RXDQ3,
+               MFP097_ETH_RXDQ2,
+               MFP098_ETH_RXDQ1,
+               MFP099_ETH_RXDQ0,
+               MFP100_ETH_MDC,
+               MFP101_ETH_MDIO,
+               MFP103_ETH_RXDV,
+
                MFP_EOC         /*End of configuration*/
        };
        /* configure MFP's */
@@ -60,3 +85,16 @@ int board_init(void)
        gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
        return 0;
 }
+
+#ifdef CONFIG_ARMADA100_FEC
+int board_eth_init(bd_t *bis)
+{
+       struct armd1apmu_registers *apmu_regs =
+               (struct armd1apmu_registers *)ARMD1_APMU_BASE;
+
+       /* Enable clock of ethernet controller */
+       writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
+
+       return armada100_fec_register(ARMD1_FEC_BASE);
+}
+#endif /* CONFIG_ARMADA100_FEC */

diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index cc14f49966dc497b6157a72e24ff6df8f1264e30..3ad2de5adbe2aff24cf0d2ea88e0cad52e2c0eda 100644 (file)
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -62,8 +62,20 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
+
+/* Disable DCACHE */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Network configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_NET_MULTI
+#define CONFIG_ARMADA100_FEC
+
+/* DHCP Support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_DHCP_REQUEST_DELAY                50000
+#endif /* CONFIG_CMD_NET */
 
 /*
  * mv-common.h should be defined after CMD configs since it used them