#define CCM_REG_CTRL_MASK 0xffffffff
#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
+#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
+#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)
#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
#define CCM_CCGR10_NFC_CTRL_MASK 0x3
+#define ANADIG_PLL7_CTRL_BYPASS (1 << 16)
+#define ANADIG_PLL7_CTRL_ENABLE (1 << 13)
+#define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12)
+#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1)
#define ANADIG_PLL5_CTRL_BYPASS (1 << 16)
#define ANADIG_PLL5_CTRL_ENABLE (1 << 13)
#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12)
#define ANADIG_PLL5_CTRL_DIV_SELECT 1
+#define ANADIG_PLL3_CTRL_BYPASS (1 << 16)
+#define ANADIG_PLL3_CTRL_ENABLE (1 << 13)
+#define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12)
+#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1)
#define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
#define ANADIG_PLL2_CTRL_DIV_SELECT 1
#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
+#define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000)
#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000)
+#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
+#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000)
--- /dev/null
+/*
+ * Freescale USB PHY Register Definitions
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __REGS_USBPHY_H__
+#define __REGS_USBPHY_H__
+
+#define USBPHY_CTRL 0x00000030
+#define USBPHY_CTRL_SET 0x00000034
+#define USBPHY_CTRL_CLR 0x00000038
+#define USBPHY_CTRL_TOG 0x0000003C
+#define USBPHY_PWD 0x00000000
+#define USBPHY_TX 0x00000010
+#define USBPHY_RX 0x00000020
+#define USBPHY_DEBUG 0x00000050
+
+#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14)
+#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15)
+#define USBPHY_CTRL_OTG_ID (1 << 27)
+#define USBPHY_CTRL_CLKGATE (1 << 30)
+#define USBPHY_CTRL_SFTRST (1 << 31)
+
+#endif /* __REGS_USBPHY_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2015 Sanchayan Maity <sanchayan.maity@toradex.com>
+ * Copyright (C) 2015 Toradex AG
+ *
+ * Based on ehci-mx6 driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <errno.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/regs-usbphy.h>
+#include <usb/ehci-fsl.h>
+
+#include "ehci.h"
+
+#define USB_NC_REG_OFFSET 0x00000800
+
+#define ANADIG_PLL_CTRL_EN_USB_CLKS (1 << 6)
+
+#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
+#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
+
+/* USBCMD */
+#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
+#define UCMD_RESET (1 << 1) /* controller reset */
+
+static const unsigned phy_bases[] = {
+ USB_PHY0_BASE_ADDR,
+ USB_PHY1_BASE_ADDR,
+};
+
+static const unsigned nc_reg_bases[] = {
+ USBC0_BASE_ADDR,
+ USBC1_BASE_ADDR,
+};
+
+static void usb_internal_phy_clock_gate(int index)
+{
+ void __iomem *phy_reg;
+
+ phy_reg = (void __iomem *)phy_bases[index];
+ clrbits_le32(phy_reg + USBPHY_CTRL, USBPHY_CTRL_CLKGATE);
+}
+
+static void usb_power_config(int index)
+{
+ struct anadig_reg __iomem *anadig =
+ (struct anadig_reg __iomem *)ANADIG_BASE_ADDR;
+ void __iomem *pll_ctrl;
+
+ switch (index) {
+ case 0:
+ pll_ctrl = &anadig->pll3_ctrl;
+ clrbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_BYPASS);
+ setbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_ENABLE
+ | ANADIG_PLL3_CTRL_POWERDOWN
+ | ANADIG_PLL_CTRL_EN_USB_CLKS);
+ break;
+ case 1:
+ pll_ctrl = &anadig->pll7_ctrl;
+ clrbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_BYPASS);
+ setbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_ENABLE
+ | ANADIG_PLL7_CTRL_POWERDOWN
+ | ANADIG_PLL_CTRL_EN_USB_CLKS);
+ break;
+ default:
+ return;
+ }
+}
+
+static void usb_phy_enable(int index, struct usb_ehci *ehci)
+{
+ void __iomem *phy_reg;
+ void __iomem *phy_ctrl;
+ void __iomem *usb_cmd;
+
+ phy_reg = (void __iomem *)phy_bases[index];
+ phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+ usb_cmd = (void __iomem *)&ehci->usbcmd;
+
+ /* Stop then Reset */
+ clrbits_le32(usb_cmd, UCMD_RUN_STOP);
+ while (readl(usb_cmd) & UCMD_RUN_STOP)
+ ;
+
+ setbits_le32(usb_cmd, UCMD_RESET);
+ while (readl(usb_cmd) & UCMD_RESET)
+ ;
+
+ /* Reset USBPHY module */
+ setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
+ udelay(10);
+
+ /* Remove CLKGATE and SFTRST */
+ clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
+ udelay(10);
+
+ /* Power up the PHY */
+ writel(0, phy_reg + USBPHY_PWD);
+
+ /* Enable FS/LS device */
+ setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
+ USBPHY_CTRL_ENUTMILEVEL3);
+}
+
+static void usb_oc_config(int index)
+{
+ void __iomem *ctrl;
+
+ ctrl = (void __iomem *)(nc_reg_bases[index] + USB_NC_REG_OFFSET);
+
+ setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
+ setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ struct usb_ehci *ehci;
+
+ if (index >= ARRAY_SIZE(nc_reg_bases))
+ return -EINVAL;
+
+ if (init == USB_INIT_DEVICE && index == 1)
+ return -ENODEV;
+ if (init == USB_INIT_HOST && index == 0)
+ return -ENODEV;
+
+ ehci = (struct usb_ehci *)nc_reg_bases[index];
+
+ usb_power_config(index);
+ usb_oc_config(index);
+ usb_internal_phy_clock_gate(index);
+ usb_phy_enable(index, ehci);
+
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+
+ if (init == USB_INIT_DEVICE) {
+ setbits_le32(&ehci->usbmode, CM_DEVICE);
+ writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
+ setbits_le32(&ehci->portsc, USB_EN);
+ } else if (init == USB_INIT_HOST) {
+ setbits_le32(&ehci->usbmode, CM_HOST);
+ writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
+ setbits_le32(&ehci->portsc, USB_EN);
+ }
+
+ return 0;
+}
+
+int ehci_hcd_stop(int index)
+{
+ return 0;
+}
projects / u-boot.git / commitdiff
