mpc83xx: Simplify BR,OR lines

Re-format all BR,OR #define lines into single lines. This makes them
harder to read, but accessible to semi-automatic replacement.

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index e19bcafd5cead364f817681b62d2fa715a2d6813..185f6490d7c6accc95bf10f99badd1560a021285 100644 (file)
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -175,19 +175,9 @@
 #define CONFIG_SYS_FLASH_BASE          0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE          8 /* FLASH size is 8M */
 
-/* Window base at flash base */
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 /* 127 64KB sectors and 8 8KB top sectors per device */
@@ -201,18 +191,9 @@
  */
 #define CONFIG_SYS_NAND_BASE   0xE0600000              /* 0xE0600000 */
 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_NAND_BASE \
-                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
-                               | BR_PS_8               /* 8 bit Port */ \
-                               | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB \
-                               | OR_FCM_CSCT \
-                               | OR_FCM_CST \
-                               | OR_FCM_CHT \
-                               | OR_FCM_SCY_1 \
-                               | OR_FCM_TRLX \
-                               | OR_FCM_EHTR)
+/* NAND */
+#define CONFIG_SYS_BR1_PRELIM  (0xE0600000 | BR_DECC_CHK_GEN   | BR_PS_8 | BR_MS_FCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
                                /* 0xFFFF8396 */
 
 #ifdef CONFIG_VSC7385_ENET
@@ -220,18 +201,9 @@
                                        /* VSC7385 Base address on CS2 */
 #define CONFIG_SYS_VSC7385_BASE                0xF0000000
 #define CONFIG_SYS_VSC7385_SIZE                (128 * 1024) /* 0x00020000 */
-#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_VSC7385_BASE \
-                                       | BR_PS_8       /* 8-bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-                                       /* 0xF0000801 */
-#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_SETA \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET)
+/* VSC7385_BASE */
+#define CONFIG_SYS_BR2_PRELIM          (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
                                        /* 0xFFFE09FF */
 /* The flash address and size of the VSC7385 firmware image */
 #define CONFIG_VSC7385_IMAGE           0xFE7FE000

diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
index bbb9d4b936cb2d45e26f2835498f9a0da1f66227..40b0264dbe421d207ccbf6650a73121398cee5e7 100644 (file)
--- a/include/configs/MPC8313ERDB_NAND.h
+++ b/include/configs/MPC8313ERDB_NAND.h
@@ -170,17 +170,6 @@
 #define CONFIG_SYS_FLASH_SIZE          8       /* flash size in MB */
 #define CONFIG_SYS_FLASH_EMPTY_INFO            /* display empty sectors */
 
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                                       | BR_PS_16      /* 16 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_9 \
-                               | OR_GPCM_EHTR \
-                               | OR_GPCM_EAD)
-                               /* 0xFF006FF7   TODO SLOW 16 MB flash size */
-
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      135     /* sectors per device */
 
@@ -230,20 +219,13 @@
 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_NAND_BASE \
-                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
-                               | BR_PS_8               /* 8 bit port */ \
-                               | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR0_PRELIM  \
-                               (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
-                               | OR_FCM_CSCT \
-                               | OR_FCM_CST \
-                               | OR_FCM_CHT \
-                               | OR_FCM_SCY_1 \
-                               | OR_FCM_TRLX \
-                               | OR_FCM_EHTR)
-                               /* 0xFFFF8396 */
+/* NAND */
+#define CONFIG_SYS_BR0_PRELIM  (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
+
+/* FLASH */
+#define CONFIG_SYS_BR1_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 /* Still needed for spl_minimal.c */
 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
@@ -253,20 +235,10 @@
 #define CONFIG_SYS_BCSR_ADDR           0xFA000000
 #define CONFIG_SYS_BCSR_SIZE           (32 * 1024)     /* 0x00008000 */
                                        /* map at 0xFA000000 on LCS3 */
-#define CONFIG_SYS_BR3_PRELIM          (CONFIG_SYS_BCSR_ADDR \
-                                       | BR_PS_8       /* 8 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-                                       /* 0xFA000801 */
-#define CONFIG_SYS_OR3_PRELIM          (OR_AM_32KB \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_ACS_DIV2 \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xFFFF8FF7 */
+/* BCSR */
+#define CONFIG_SYS_BR3_PRELIM          (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR3_PRELIM          (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
+
 /* Vitesse 7385 */
 
 #ifdef CONFIG_VSC7385_ENET
@@ -275,19 +247,10 @@
 #define CONFIG_SYS_VSC7385_BASE                0xF0000000
 #define CONFIG_SYS_VSC7385_SIZE                (128 * 1024)    /* 0x00020000 */
 
-#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_VSC7385_BASE \
-                                       | BR_PS_8       /* 8 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_SETA \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xFFFE09FF */
+/* VSC7385 */
+#define CONFIG_SYS_BR2_PRELIM          (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
+
 #endif
 
 #define CONFIG_MPC83XX_GPIO 1

diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
index 1cb001864a4e7b1a6e6352292912746be5fd4784..390ee4eb265357da7463367778c1e2e03595ee09 100644 (file)
--- a/include/configs/MPC8313ERDB_NOR.h
+++ b/include/configs/MPC8313ERDB_NOR.h
@@ -143,17 +143,6 @@
 #define CONFIG_SYS_FLASH_PROTECTION    1       /* Use h/w Flash protection. */
 #define CONFIG_SYS_FLASH_EMPTY_INFO            /* display empty sectors */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                                       | BR_PS_16      /* 16 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_9 \
-                               | OR_GPCM_EHTR \
-                               | OR_GPCM_EAD)
-                               /* 0xFF006FF7   TODO SLOW 16 MB flash size */
-
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      135     /* sectors per device */
 
@@ -199,20 +188,13 @@
 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_NAND_BASE \
-                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
-                               | BR_PS_8               /* 8 bit port */ \
-                               | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR1_PRELIM  \
-                               (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
-                               | OR_FCM_CSCT \
-                               | OR_FCM_CST \
-                               | OR_FCM_CHT \
-                               | OR_FCM_SCY_1 \
-                               | OR_FCM_TRLX \
-                               | OR_FCM_EHTR)
-                               /* 0xFFFF8396 */
+/* FLASH*/
+#define CONFIG_SYS_BR0_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
+
+/* NAND */
+#define CONFIG_SYS_BR1_PRELIM  (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
 
 /* Still needed for spl_minimal.c */
 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
@@ -222,20 +204,9 @@
 #define CONFIG_SYS_BCSR_ADDR           0xFA000000
 #define CONFIG_SYS_BCSR_SIZE           (32 * 1024)     /* 0x00008000 */
                                        /* map at 0xFA000000 on LCS3 */
-#define CONFIG_SYS_BR3_PRELIM          (CONFIG_SYS_BCSR_ADDR \
-                                       | BR_PS_8       /* 8 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-                                       /* 0xFA000801 */
-#define CONFIG_SYS_OR3_PRELIM          (OR_AM_32KB \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_ACS_DIV2 \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xFFFF8FF7 */
+/* BCSR */
+#define CONFIG_SYS_BR3_PRELIM          (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR3_PRELIM          (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 /* Vitesse 7385 */
 
 #ifdef CONFIG_VSC7385_ENET
@@ -244,19 +215,10 @@
 #define CONFIG_SYS_VSC7385_BASE                0xF0000000
 #define CONFIG_SYS_VSC7385_SIZE                (128 * 1024)    /* 0x00020000 */
 
-#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_VSC7385_BASE \
-                                       | BR_PS_8       /* 8 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_SETA \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xFFFE09FF */
+/* VSC7385 */
+#define CONFIG_SYS_BR2_PRELIM          (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
+
 #endif
 
 #define CONFIG_MPC83XX_GPIO 1

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 86491b41d66ac7c438e4306cc8f18bd21672e0bd..97b66415c9ba89a80f3bf2994cd602001bce0ef5 100644 (file)
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -177,33 +177,13 @@
 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
-                                       | BR_PS_16      /* 16 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
-                                       | OR_UPM_XAM \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_ACS_DIV2 \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
-                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
-                               | BR_PS_8               /* 8 bit port */ \
-                               | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR1_PRELIM \
-                               (OR_AM_32KB \
-                               | OR_FCM_CSCT \
-                               | OR_FCM_CST \
-                               | OR_FCM_CHT \
-                               | OR_FCM_SCY_1 \
-                               | OR_FCM_TRLX \
-                               | OR_FCM_EHTR)
-                               /* 0xFFFF8396 */
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
+
+/* NAND */
+#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
 
 /* Still needed for spl_minimal.c */
 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM

diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 30f1e4453d167f83534733db92302cfda32cc265..fd884a1e654d885a7ca7e21c4e6c633efdfcd20b 100644 (file)
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -142,20 +142,9 @@
 #define CONFIG_SYS_FLASH_SIZE          16      /* FLASH size is 16M */
 
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_16MB \
-                               | OR_GPCM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xFE006FF7 */
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      128     /* sectors per device */

diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 3a8a3e4fb89875479587de2677f7936a2aa47ca8..41b0223135242fc890898c78ee1d19e214254ab4 100644 (file)
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -133,20 +133,9 @@
 #define CONFIG_SYS_FLASH_BASE  0xFE000000      /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE  16      /* FLASH size is 16M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_16MB \
-                               | OR_GPCM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xfe006ff7 */
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      128     /* sectors per device */
@@ -159,19 +148,9 @@
 #define CONFIG_SYS_BCSR                        0xF8000000
                                        /* Access window base at BCSR base */
 
-#define CONFIG_SYS_BR1_PRELIM          (CONFIG_SYS_BCSR \
-                                       | BR_PS_8 \
-                                       | BR_MS_GPCM \
-                                       | BR_V)
-#define CONFIG_SYS_OR1_PRELIM          (OR_AM_32KB \
-                                       | OR_GPCM_XAM \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xFFFFE9F7 */
+/* BCSR */
+#define CONFIG_SYS_BR1_PRELIM          (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM          (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 /*
  * Windows to access PIB via local bus
@@ -183,39 +162,18 @@
 /*
  * CS2 on Local Bus, to PIB
  */
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_PIB_BASE \
-                               | BR_PS_8 \
-                               | BR_MS_GPCM \
-                               | BR_V)
-                               /* 0xF8008801 */
-#define CONFIG_SYS_OR2_PRELIM  (OR_AM_32KB \
-                               | OR_GPCM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xffffe9f7 */
+
+/* PIB1 */
+#define CONFIG_SYS_BR2_PRELIM  (0xF8008000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 /*
  * CS3 on Local Bus, to PIB
  */
-#define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_PIB_BASE + \
-                                       CONFIG_SYS_PIB_WINDOW_SIZE) \
-                               | BR_PS_8 \
-                               | BR_MS_GPCM \
-                               | BR_V)
-                               /* 0xF8010801 */
-#define CONFIG_SYS_OR3_PRELIM  (OR_AM_32KB \
-                               | OR_GPCM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xffffe9f7 */
+
+/* PIB2 */
+#define CONFIG_SYS_BR3_PRELIM  (0xF8010000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index fa73b81c3a0b96f4fb98bf1e8509d149c39b3c00..4cda1589b676f09673fe52c2ddc75353af49c428 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -123,19 +123,9 @@
 #define CONFIG_SYS_FLASH_BASE          0xFE000000      /* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE          32      /* max flash size in MB */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port  */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_32MB \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      256     /* max sectors per device */
@@ -157,18 +147,10 @@
  */
 #define CONFIG_SYS_BCSR                        0xE2400000
                                        /* Access window base at BCSR base */
-#define CONFIG_SYS_BR1_PRELIM          (CONFIG_SYS_BCSR \
-                                       | BR_PS_8 \
-                                       | BR_MS_GPCM \
-                                       | BR_V)
-                                       /* 0x00000801 */
-#define CONFIG_SYS_OR1_PRELIM          (OR_AM_32KB \
-                                       | OR_GPCM_XAM \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_CLEAR \
-                                       | OR_GPCM_EHTR_CLEAR)
-                                       /* 0xFFFFE8F0 */
+
+/* BCSR */
+#define CONFIG_SYS_BR1_PRELIM          (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM          (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000      /* Initial RAM addr */

diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index 218c4b1fc98a52b4853c250b24df83d55e7d3421..7f906c38d899ee3d6c968bf565378ba48dea4b15 100644 (file)
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -123,19 +123,9 @@
 #define CONFIG_SYS_FLASH_BASE          0xFE000000      /* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE          32      /* max flash size in MB */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port  */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_32MB \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      256     /* max sectors per device */
@@ -157,18 +147,9 @@
  */
 #define CONFIG_SYS_BCSR                        0xE2400000
                                        /* Access window base at BCSR base */
-#define CONFIG_SYS_BR1_PRELIM          (CONFIG_SYS_BCSR \
-                                       | BR_PS_8 \
-                                       | BR_MS_GPCM \
-                                       | BR_V)
-                                       /* 0x00000801 */
-#define CONFIG_SYS_OR1_PRELIM          (OR_AM_32KB \
-                                       | OR_GPCM_XAM \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_CLEAR \
-                                       | OR_GPCM_EHTR_CLEAR)
-                                       /* 0xFFFFE8F0 */
+/* BCSR */
+#define CONFIG_SYS_BR1_PRELIM          (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM          (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000      /* Initial RAM addr */
@@ -211,11 +192,9 @@
  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
  */
 
-#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_LBC_SDRAM_BASE \
-                                       | BR_PS_32      /* 32-bit port */ \
-                                       | BR_MS_SDRAM   /* MSEL = SDRAM */ \
-                                       | BR_V)         /* Valid */
-                                       /* 0xF0001861 */
+/* SDRAM */
+#define CONFIG_SYS_BR2_PRELIM  (0xF0000000 | BR_PS_32 | BR_MS_SDRAM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_64MB | OR_SDRAM_XAM | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) | OR_SDRAM_EAD)
 
 /*
  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
@@ -231,12 +210,6 @@
  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
  */
 
-#define CONFIG_SYS_OR2_PRELIM  (OR_AM_64MB \
-                       | OR_SDRAM_XAM \
-                       | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
-                       | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
-                       | OR_SDRAM_EAD)
-                       /* 0xFC006901 */
 
                                /* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_LSRT    0x32000000

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 0bf179a70b146a21b1b9033a719b72a8255b49c1..e90d497f5ef84bdd0f1402445d57189a13253890 100644 (file)
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -211,56 +211,28 @@ boards, we say we have two, but don't display a message if we find only one. */
  * BRx, ORx, LBLAWBARx, and LBLAWARx
  */
 
-/* Flash */
-
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16 \
-                               | BR_MS_GPCM \
-                               | BR_V)
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_16MB \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_16MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
+
 /* Vitesse 7385 */
 
 #define CONFIG_SYS_VSC7385_BASE        0xF8000000
 
 #ifdef CONFIG_VSC7385_ENET
 
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_VSC7385_BASE \
-                               | BR_PS_8 \
-                               | BR_MS_GPCM \
-                               | BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128KB \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_SETA \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
+/* VSC7385 */
+#define CONFIG_SYS_BR1_PRELIM  (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
+
 #endif
 
-/* LED */
 
 #define CONFIG_SYS_LED_BASE    0xF9000000
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_LED_BASE \
-                               | BR_PS_8 \
-                               | BR_MS_GPCM \
-                               | BR_V)
-#define CONFIG_SYS_OR2_PRELIM  (OR_AM_2MB \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_9 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
+
+/* LED */
+#define CONFIG_SYS_BR2_PRELIM  (0xF9000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 /* Compact Flash */
 
@@ -268,11 +240,9 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #define CONFIG_SYS_CF_BASE     0xF0000000
 
-#define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_CF_BASE \
-                               | BR_PS_16 \
-                               | BR_MS_UPMA \
-                               | BR_V)
-#define CONFIG_SYS_OR3_PRELIM  (OR_UPM_AM | OR_UPM_BI)
+/* CF */
+#define CONFIG_SYS_BR3_PRELIM  (0xF0000000 | BR_PS_16 | BR_MS_UPMA | BR_V)
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_32KB | OR_UPM_BI)
 
 #endif
 

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index e10c58d7eda5c8d53a3c29e85823399370d2909a..e569e63741f3159e17270441e03ec5c7c204dbc4 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -162,20 +162,9 @@
 #define CONFIG_SYS_FLASH_BASE  0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE  32 /* max FLASH size is 32M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_32MB \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xFE000FF7 */
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      256 /* max sectors per device */
@@ -189,20 +178,9 @@
  */
 #define CONFIG_SYS_BCSR                0xF8000000
                                        /* Access window base at BCSR base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_BCSR \
-                               | BR_PS_8 \
-                               | BR_MS_GPCM \
-                               | BR_V)
-                               /* 0xF8000801 */
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB \
-                               | OR_GPCM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xFFFFE9F7 */
+/* BCSR */
+#define CONFIG_SYS_BR1_PRELIM  (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 /*
  * NAND Flash on the Local Bus
@@ -211,20 +189,10 @@
 #define CONFIG_NAND_FSL_ELBC   1
 
 #define CONFIG_SYS_NAND_BASE   0xE0600000
-#define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_NAND_BASE \
-                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
-                               | BR_PS_8               /* 8 bit port */ \
-                               | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR3_PRELIM  (OR_AM_32KB \
-                               | OR_FCM_BCTLD \
-                               | OR_FCM_CST \
-                               | OR_FCM_CHT \
-                               | OR_FCM_SCY_1 \
-                               | OR_FCM_RST \
-                               | OR_FCM_TRLX \
-                               | OR_FCM_EHTR)
-                               /* 0xFFFF919E */
+
+/* NAND */
+#define CONFIG_SYS_BR3_PRELIM  (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST | OR_FCM_TRLX | OR_FCM_EHTR)
 
 /*
  * Serial Port

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 1e45b5ee3f159615ff443e654ad237e40b8eb329..c1898a53a6c737d2241476f364f28c7de1b03a55 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -188,16 +188,9 @@
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO            /* display empty sectors */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_9 \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xFF800191 */
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      256 /* max sectors per device */
@@ -210,38 +203,21 @@
  * NAND Flash on the Local Bus
  */
 #define CONFIG_SYS_NAND_BASE   0xE0600000
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_NAND_BASE \
-                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
-                               | BR_PS_8               /* 8 bit port */ \
-                               | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB \
-                               | OR_FCM_CSCT \
-                               | OR_FCM_CST \
-                               | OR_FCM_CHT \
-                               | OR_FCM_SCY_1 \
-                               | OR_FCM_TRLX \
-                               | OR_FCM_EHTR)
+
+/* NAND */
+#define CONFIG_SYS_BR1_PRELIM  (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
+
 /* Vitesse 7385 */
 
 #define CONFIG_SYS_VSC7385_BASE        0xF0000000
 
 #ifdef CONFIG_VSC7385_ENET
 
-#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_VSC7385_BASE \
-                                       | BR_PS_8 \
-                                       | BR_MS_GPCM \
-                                       | BR_V)
-                                       /* 0xF0000801 */
-#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_SETA \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xfffe09ff */
+/* VSC7385 */
+#define CONFIG_SYS_BR2_PRELIM          (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
+
 #endif
 
 /*

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 4479000d25acf4d4c2eba7cfd261d41f63a97356..c76df2847d287e020207b290068193a270124d9f 100644 (file)
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -76,22 +76,9 @@
 
 #define CONFIG_SYS_MAX_FLASH_SECT      512     /* max sectors per device */
 
-/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
-#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BR_BA) \
-                               | BR_MS_GPCM \
-                               | BR_PS_32 \
-                               | BR_V)
-
-/* FLASH timing (0x0000_0c54) */
-#define CONFIG_SYS_OR_TIMING_FLASH     (OR_GPCM_CSNT \
-                                       | OR_GPCM_ACS_DIV4 \
-                                       | OR_GPCM_SCY_5 \
-                                       | OR_GPCM_TRLX)
-
-#define CONFIG_SYS_PRELIM_OR_AM                OR_AM_1GB /* OR addr mask: 1 GiB */
-
-#define CONFIG_SYS_OR0_PRELIM          (CONFIG_SYS_PRELIM_OR_AM  \
-                                       | CONFIG_SYS_OR_TIMING_FLASH)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0x80000000 | BR_MS_GPCM | BR_PS_32 | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_1GB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET)
 
 /* disable remaining mappings */
 #define CONFIG_SYS_BR1_PRELIM          0x00000000

diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
index ffd52a200a32c2ae2c640432e2c830c7175e89bf..a7eb5f529539e5d61a713e4a2526b1c18c1d5e78 100644 (file)
--- a/include/configs/caddy2.h
+++ b/include/configs/caddy2.h
@@ -69,31 +69,16 @@
  */
 #define CONFIG_SYS_FLASH_BASE          0xffc00000      /* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE          4               /* flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM          (CONFIG_SYS_FLASH_BASE | \
-                                        BR_PS_16 |     /*  16bit */ \
-                                        BR_MS_GPCM |   /*  MSEL = GPCM */ \
-                                        BR_V)          /* valid */
-
-#define CONFIG_SYS_OR0_PRELIM          (OR_AM_4MB \
-                                       | OR_GPCM_XAM \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_ACS_DIV2 \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xffc06ff7 */
+
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM          (0xFFC00000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM          (OR_AM_4MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_WINDOW1_BASE                0xf0000000
-#define CONFIG_SYS_BR1_PRELIM          (CONFIG_SYS_WINDOW1_BASE \
-                                       | BR_PS_32 \
-                                       | BR_MS_GPCM \
-                                       | BR_V)
-                                       /* 0xF0001801 */
-#define CONFIG_SYS_OR1_PRELIM          (OR_AM_256KB \
-                                       | OR_GPCM_SETA)
-                                       /* 0xfffc0208 */
+
+/* WINDOW1 */
+#define CONFIG_SYS_BR1_PRELIM          (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM          (OR_AM_256KB | OR_GPCM_SETA)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device*/

diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 4193ceb3793f14c5cb8637c20007c95cff350880..3fe72db188cdc055ee33d7a463de621e29713cf5 100644 (file)
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -169,19 +169,9 @@
 #define CONFIG_SYS_FLASH_BASE          0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE          8 /* FLASH size is up to 8M */
 
-/* Window base at flash base */
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      135
@@ -195,19 +185,9 @@
 #define CONFIG_SYS_FPGA0_BASE          0xE0600000
 #define CONFIG_SYS_FPGA0_SIZE          1 /* FPGA size is 1M */
 
-/* Window base at FPGA base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_FPGA0_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_1MB \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET)
+/* FPGA */
+#define CONFIG_SYS_BR1_PRELIM  (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
 
 #define CONFIG_SYS_FPGA_BASE(k)                CONFIG_SYS_FPGA0_BASE
 #define CONFIG_SYS_FPGA_DONE(k)                0x0010

diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 871b91f2183effc1bf57491fe3fbf3b0076d6710..61f64ebbbc07b5fd1c5e547e6e45398b5e18ec73 100644 (file)
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -142,17 +142,10 @@
 #define CONFIG_SYS_FLASH_BASE          0xFF800000
 #define CONFIG_SYS_FLASH_SIZE          8
 
-#define CONFIG_SYS_BR0_PRELIM          (CONFIG_SYS_FLASH_BASE |\
-                                        BR_PS_8 |\
-                                        BR_MS_GPCM |\
-                                        BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM          (OR_AM_8MB |\
-                                        OR_GPCM_SCY_10 |\
-                                        OR_GPCM_EHTR |\
-                                        OR_GPCM_TRLX |\
-                                        OR_GPCM_CSNT |\
-                                        OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM          (0xFF800000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM          (OR_AM_8MB | OR_GPCM_SCY_10 | OR_GPCM_EHTR_SET | OR_GPCM_TRLX_SET | OR_GPCM_CSNT | OR_GPCM_EAD)
+
 #define CONFIG_SYS_MAX_FLASH_BANKS     1
 #define CONFIG_SYS_MAX_FLASH_SECT      128
 
@@ -170,21 +163,9 @@
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (128 << 10)
 #define NAND_CACHE_PAGES               64
 
-#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_NAND_BASE) |\
-                                BR_DECC_CHK_GEN |\
-                                BR_PS_8 |\
-                                BR_MS_FCM |\
-                                BR_V)
-
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB |\
-                                OR_FCM_PGS |\
-                                OR_FCM_CSCT |\
-                                OR_FCM_CST |\
-                                OR_FCM_CHT |\
-                                OR_FCM_SCY_4 |\
-                                OR_FCM_TRLX |\
-                                OR_FCM_EHTR |\
-                                OR_FCM_RST)
+/* NAND */
+#define CONFIG_SYS_BR1_PRELIM  (0xE1000000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_4 | OR_FCM_TRLX | OR_FCM_EHTR | OR_FCM_RST)
 
 /*
  * MRAM setup
@@ -194,11 +175,8 @@
 
 #define CONFIG_SYS_OR_TIMING_MRAM
 
-#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_MRAM_BASE |\
-                                        BR_PS_8 |\
-                                        BR_MS_GPCM |\
-                                        BR_V)
-
+/* MRAM */
+#define CONFIG_SYS_BR2_PRELIM          (0xE2000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
 #define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET)
 
 /*
@@ -209,11 +187,8 @@
 
 #define CONFIG_SYS_OR_TIMING_MRAM
 
-#define CONFIG_SYS_BR3_PRELIM          (CONFIG_SYS_CPLD_BASE |\
-                                        BR_PS_8 |\
-                                        BR_MS_GPCM |\
-                                        BR_V)
-
+/* CPLD */
+#define CONFIG_SYS_BR3_PRELIM          (0xE3000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
 #define CONFIG_SYS_OR3_PRELIM          (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET)
 
 /*

diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index 370e6b496aea24838bdf228dd6564b0b9e41e4b3..5027073d6e97006fe1103c4467bda4b370c7a69c 100644 (file)
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h
@@ -108,15 +108,9 @@
  */
 #define CONFIG_SYS_FLASH_SIZE          256 /* max FLASH size is 256M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | \
-                               BR_PS_16 | /* 16 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_5 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -125,15 +119,10 @@
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
-/* Window base at flash base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_KMBEC_FPGA_BASE | \
-                               BR_PS_8 | /* 8 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_64MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_2 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+
+/* KMBEC_FPGA */
+#define CONFIG_SYS_BR1_PRELIM  (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -347,18 +336,9 @@
 #define CONFIG_SYS_PAXE_BASE           0xA0000000
 #define CONFIG_SYS_PAXE_SIZE           256
 
-#define CONFIG_SYS_BR3_PRELIM (\
-       CONFIG_SYS_PAXE_BASE | \
-       BR_PS_8 | \
-       BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM (\
-       OR_AM_256MB | \
-       OR_GPCM_CSNT | \
-       OR_GPCM_ACS_DIV2 | \
-       OR_GPCM_SCY_2 | \
-       OR_GPCM_TRLX | \
-       OR_GPCM_EAD)
+/* PAXE */
+#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * BFTIC3 on the local bus CS4
@@ -366,18 +346,9 @@
 #define CONFIG_SYS_BFTIC3_BASE                 0xB0000000
 #define CONFIG_SYS_BFTIC3_SIZE                 256
 
-#define CONFIG_SYS_BR4_PRELIM (\
-       CONFIG_SYS_BFTIC3_BASE |\
-       BR_PS_8 | \
-       BR_V)
-
-#define CONFIG_SYS_OR4_PRELIM (\
-       OR_AM_256MB|\
-       OR_GPCM_CSNT | \
-       OR_GPCM_ACS_DIV2 |\
-       OR_GPCM_SCY_2 |\
-       OR_GPCM_TRLX |\
-       OR_GPCM_EAD)
+/* BFTIC3 */
+#define CONFIG_SYS_BR4_PRELIM (0xB0000000 | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR4_PRELIM (OR_AM_256MB| OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /* enable POST tests */
 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)

diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 2650544305c731e1634a3d662a927a7b79b152a1..84516bb9bb7c62724c05190886a563c8f1d9137a 100644 (file)
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -93,15 +93,9 @@
  */
 #define CONFIG_SYS_FLASH_SIZE          256 /* max FLASH size is 256M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | \
-                               BR_PS_16 | /* 16 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_5 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -110,15 +104,10 @@
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
-/* Window base at flash base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_KMBEC_FPGA_BASE | \
-                               BR_PS_8 | /* 8 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_64MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_2 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+
+/* KMBEC_FPGA */
+#define CONFIG_SYS_BR1_PRELIM  (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -327,17 +316,8 @@
 #define CONFIG_SYS_PAXE_BASE           0xA0000000
 #define CONFIG_SYS_PAXE_SIZE           256
 
-#define CONFIG_SYS_BR3_PRELIM (\
-       CONFIG_SYS_PAXE_BASE | \
-       BR_PS_8 | \
-       BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM (\
-       OR_AM_256MB | \
-       OR_GPCM_CSNT | \
-       OR_GPCM_ACS_DIV2 | \
-       OR_GPCM_SCY_2 | \
-       OR_GPCM_TRLX | \
-       OR_GPCM_EAD)
+/* PAXE */
+#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #endif /* CONFIG */

diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h
index 6e59fde6bd0736e8c04b2362ccc1766d386d03ec..678cb6a7cc7b8c14039369c1c9ef330eae8559d8 100644 (file)
--- a/include/configs/kmopti2.h
+++ b/include/configs/kmopti2.h
@@ -113,15 +113,9 @@
  */
 #define CONFIG_SYS_FLASH_SIZE          256 /* max FLASH size is 256M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | \
-                               BR_PS_16 | /* 16 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_5 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -130,15 +124,10 @@
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
-/* Window base at flash base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_KMBEC_FPGA_BASE | \
-                               BR_PS_8 | /* 8 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_2 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+
+/* KMBEC_FPGA */
+#define CONFIG_SYS_BR1_PRELIM  (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -361,29 +350,17 @@
 /*
  * Configuration for C2 on the local bus
  */
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_APP1_BASE | \
-                                BR_PS_8 | \
-                                BR_MS_GPCM | \
-                                BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | \
-                                OR_GPCM_CSNT | \
-                                OR_GPCM_ACS_DIV4 | \
-                                OR_GPCM_SCY_2 | \
-                                OR_GPCM_TRLX_SET | \
-                                OR_GPCM_EHTR_CLEAR | \
-                                OR_GPCM_EAD)
+
+/* APP1 */
+#define CONFIG_SYS_BR2_PRELIM  (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
 
 /*
  * Configuration for C3 on the local bus
  */
-#define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_APP2_BASE | \
-                                BR_PS_16 |             \
-                                BR_MS_GPCM |           \
-                                BR_V)
-#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | \
-                                OR_GPCM_SCY_4 | \
-                                OR_GPCM_TRLX_CLEAR | \
-                                OR_GPCM_EHTR_CLEAR)
+
+/* APP2 */
+#define CONFIG_SYS_BR3_PRELIM  (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
index af39e8bb857e1046b50cce305feadd4e1c07bf6a..3e2e425c34b10908173ca4f27c5ec560dc45fbf7 100644 (file)
--- a/include/configs/kmsupx5.h
+++ b/include/configs/kmsupx5.h
@@ -113,15 +113,9 @@
  */
 #define CONFIG_SYS_FLASH_SIZE          256 /* max FLASH size is 256M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | \
-                               BR_PS_16 | /* 16 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_5 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -130,15 +124,10 @@
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
-/* Window base at flash base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_KMBEC_FPGA_BASE | \
-                               BR_PS_8 | /* 8 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_2 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+
+/* KMBEC_FPGA */
+#define CONFIG_SYS_BR1_PRELIM  (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -356,20 +345,8 @@
  *  3   Local   GPCM    8 bit  256MB  TEP2 (16 bit)
  */
 
-/*
- * Configuration for C2 on the local bus
- */
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_APP1_BASE | \
-                                BR_PS_8 | \
-                                BR_MS_GPCM | \
-                                BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | \
-                                OR_GPCM_CSNT | \
-                                OR_GPCM_ACS_DIV4 | \
-                                OR_GPCM_SCY_2 | \
-                                OR_GPCM_TRLX_SET | \
-                                OR_GPCM_EHTR_CLEAR | \
-                                OR_GPCM_EAD)
+/* APP1 */
+#define CONFIG_SYS_BR2_PRELIM  (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
index 1312aa2fa998b4933ef989551002c9e33d0168a1..ed221e230195ca78b01f4aacf49f337e2c8e18ba 100644 (file)
--- a/include/configs/kmtegr1.h
+++ b/include/configs/kmtegr1.h
@@ -120,15 +120,9 @@
  */
 #define CONFIG_SYS_FLASH_SIZE          256 /* max FLASH size is 256M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | \
-                               BR_PS_16 | /* 16 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_5 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -137,15 +131,10 @@
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
-/* Window base at flash base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_KMBEC_FPGA_BASE | \
-                               BR_PS_8 | /* 8 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_2 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+
+/* KMBEC_FPGA */
+#define CONFIG_SYS_BR1_PRELIM  (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -411,15 +400,9 @@
  *
  */
 
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
-                                BR_PS_16 | \
-                                BR_MS_GPCM | \
-                                BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | \
-                                OR_GPCM_SCY_5 | \
-                                OR_GPCM_TRLX_CLEAR | \
-                                OR_GPCM_EHTR_CLEAR)
+/* APP2 */
+#define CONFIG_SYS_BR3_PRELIM  (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
 
 /* ethernet port connected to piggy (UEC2) */
 #define CONFIG_HAS_ETH1

diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h
index fd00ea86a98883c6a594e016123c004c78f3bdef..c1ed71e2afebdc75953073a3f260c9234a7e89e7 100644 (file)
--- a/include/configs/kmtepr2.h
+++ b/include/configs/kmtepr2.h
@@ -113,15 +113,9 @@
  */
 #define CONFIG_SYS_FLASH_SIZE          256 /* max FLASH size is 256M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | \
-                               BR_PS_16 | /* 16 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_5 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -130,15 +124,10 @@
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
-/* Window base at flash base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_KMBEC_FPGA_BASE | \
-                               BR_PS_8 | /* 8 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_2 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+
+/* KMBEC_FPGA */
+#define CONFIG_SYS_BR1_PRELIM  (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -358,32 +347,12 @@
  *  3   Local   GPCM    8 bit  256MB  TEP2 (16 bit)
  */
 
-/*
- * Configuration for C2 on the local bus
- */
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_APP1_BASE | \
-                                BR_PS_8 | \
-                                BR_MS_GPCM | \
-                                BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | \
-                                OR_GPCM_CSNT | \
-                                OR_GPCM_ACS_DIV4 | \
-                                OR_GPCM_SCY_2 | \
-                                OR_GPCM_TRLX_SET | \
-                                OR_GPCM_EHTR_CLEAR | \
-                                OR_GPCM_EAD)
+/* APP1 */
+#define CONFIG_SYS_BR2_PRELIM  (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
 
-/*
- * Configuration for C3 on the local bus
- */
-#define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_APP2_BASE | \
-                                BR_PS_16 |             \
-                                BR_MS_GPCM |           \
-                                BR_V)
-#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | \
-                                OR_GPCM_SCY_4 | \
-                                OR_GPCM_TRLX_CLEAR | \
-                                OR_GPCM_EHTR_CLEAR)
+/* APP2 */
+#define CONFIG_SYS_BR3_PRELIM  (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h
index 3d9164714c7725634a1ba0f16d81074a98f5f3f8..406b6e782441c3f68239d464ddbd7d3e2143a6e5 100644 (file)
--- a/include/configs/kmvect1.h
+++ b/include/configs/kmvect1.h
@@ -112,15 +112,9 @@
  */
 #define CONFIG_SYS_FLASH_SIZE          256 /* max FLASH size is 256M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | \
-                               BR_PS_16 | /* 16 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_5 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -129,15 +123,10 @@
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
-/* Window base at flash base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_KMBEC_FPGA_BASE | \
-                               BR_PS_8 | /* 8 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_2 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+
+/* KMBEC_FPGA */
+#define CONFIG_SYS_BR1_PRELIM  (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -400,24 +389,13 @@
  *
  */
 
-/*
- * APP1 on the local bus CS2
- */
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_APP1_BASE | \
-                                BR_PS_16 | \
-                                BR_MS_UPMA | \
-                                BR_V)
+/* APP1 */
+#define CONFIG_SYS_BR2_PRELIM  (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V)
 #define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB)
 
-#define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_APP2_BASE | \
-                                BR_PS_16 | \
-                                BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | \
-                                OR_GPCM_CSNT | \
-                                OR_GPCM_ACS_DIV4 | \
-                                OR_GPCM_SCY_3 | \
-                                OR_GPCM_TRLX_SET)
+/* APP2 */
+#define CONFIG_SYS_BR3_PRELIM  (0xB0000000 | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET)
 
 #define CONFIG_SYS_MAMR        (MxMR_GPL_x4DIS | \
                         0x0000c000 | \

diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 046355f64547d7bb2c0807ef039aec3dee8a7407..31bf9971ab2225cc38ac24caba1be6bc60329b91 100644 (file)
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -179,19 +179,9 @@
 #define CONFIG_SYS_FLASH_BASE          0xFC000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE          64 /* FLASH size is 64M */
 
-/* Window base at flash base */
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_64MB \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_4 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xFC000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_64MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_4 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      512
@@ -205,27 +195,19 @@
  * SJA1000 CAN controller on Local Bus
  */
 #define CONFIG_SYS_SJA1000_BASE        0xFBFF0000
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_SJA1000_BASE \
-                               | BR_PS_8       /* 8 bit port size */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB \
-                               | OR_GPCM_SCY_5 \
-                               | OR_GPCM_EHTR_SET)
-                               /* 0xFFFF8052 */
+
+/* SJA1000 */
+#define CONFIG_SYS_BR1_PRELIM  (0xFBFF0000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_GPCM_SCY_5 | OR_GPCM_EHTR_SET)
 
 /*
  * CPLD on Local Bus
  */
 #define CONFIG_SYS_CPLD_BASE   0xFBFF8000
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_CPLD_BASE \
-                               | BR_PS_8       /* 8 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR2_PRELIM  (OR_AM_32KB \
-                               | OR_GPCM_SCY_4 \
-                               | OR_GPCM_EHTR_SET)
-                               /* 0xFFFF8042 */
+
+/* CPLD */
+#define CONFIG_SYS_BR2_PRELIM  (0xFBFF8000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_32KB | OR_GPCM_SCY_4 | OR_GPCM_EHTR_SET)
 
 /*
  * Serial Port

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index dffb7c61086571f7d1bab892bc1b11c2167db1d8..09cdb7c1a8a407c6e90e732412ab78b44a82485e 100644 (file)
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -98,21 +98,9 @@
 #define CONFIG_SYS_FLASH_BASE          0xFF800000      /* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE          8               /* flash size in MB */
 
-#define CONFIG_SYS_BR0_PRELIM          (CONFIG_SYS_FLASH_BASE \
-                                       | BR_PS_16      /* 16 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-
-#define CONFIG_SYS_OR0_PRELIM          (OR_AM_8MB \
-                                       | OR_GPCM_XAM \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_ACS_DIV2 \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xFF806FF7 */
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM          (0xFF800000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM          (OR_AM_8MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      64      /* sectors per device */

diff --git a/include/configs/strider.h b/include/configs/strider.h
index 184396e0379ced3af93e4916b20d418d6bf4ce13..1519dad3217177c844296e04f08cc3eeb83a2410 100644 (file)
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -167,19 +167,9 @@
 #define CONFIG_SYS_FLASH_BASE          0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE          8 /* FLASH size is up to 8M */
 
-/* Window base at flash base */
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      135
@@ -193,18 +183,9 @@
 #define CONFIG_SYS_FPGA0_BASE          0xE0600000
 #define CONFIG_SYS_FPGA0_SIZE          1 /* FPGA size is 1M */
 
-/* Window base at FPGA base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_FPGA0_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-
-#define CONFIG_SYS_OR1_PRELIM   (OR_AM_1MB \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_SCY_5 \
-                               | OR_GPCM_TRLX_CLEAR \
-                               | OR_GPCM_EHTR_CLEAR)
+/* FPGA */
+#define CONFIG_SYS_BR1_PRELIM  (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM   (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_SYS_FPGA_BASE(k)                CONFIG_SYS_FPGA0_BASE
 #define CONFIG_SYS_FPGA_DONE(k)                0x0010

diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index ad270de87d736f7daf8fc7cee273427d1ad2e4dc..6aacbc2077ee4974337aee0c5a5ae030c4556057 100644 (file)
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -110,15 +110,9 @@
  */
 #define CONFIG_SYS_FLASH_SIZE          256 /* max FLASH size is 256M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | \
-                               BR_PS_16 | /* 16 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_5 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -127,15 +121,10 @@
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
-/* Window base at flash base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_KMBEC_FPGA_BASE | \
-                               BR_PS_8 | /* 8 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_2 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+
+/* KMBEC_FPGA */
+#define CONFIG_SYS_BR1_PRELIM  (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -353,24 +342,13 @@
  *
  */
 
-/*
- * APP1 on the local bus CS2
- */
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_APP1_BASE | \
-                                BR_PS_16 | \
-                                BR_MS_UPMA | \
-                                BR_V)
+/* APP1 */
+#define CONFIG_SYS_BR2_PRELIM  (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V)
 #define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB)
 
-#define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_APP2_BASE | \
-                                BR_PS_16 | \
-                                BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | \
-                                OR_GPCM_CSNT | \
-                                OR_GPCM_ACS_DIV4 | \
-                                OR_GPCM_SCY_3 | \
-                                OR_GPCM_TRLX_SET)
+/* APP2 */
+#define CONFIG_SYS_BR3_PRELIM  (0xB0000000 | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET)
 
 #define CONFIG_SYS_MAMR        (MxMR_GPL_x4DIS | \
                         0x0000c000 | \

diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h
index af6a348ba579cebc965eda8c118f062cab31e694..b11d49629ac329eecd20906bf47d8da6e23c7d27 100644 (file)
--- a/include/configs/tuge1.h
+++ b/include/configs/tuge1.h
@@ -113,15 +113,9 @@
  */
 #define CONFIG_SYS_FLASH_SIZE          256 /* max FLASH size is 256M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | \
-                               BR_PS_16 | /* 16 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_5 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -130,15 +124,10 @@
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
-/* Window base at flash base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_KMBEC_FPGA_BASE | \
-                               BR_PS_8 | /* 8 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_2 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+
+/* KMBEC_FPGA */
+#define CONFIG_SYS_BR1_PRELIM  (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -356,20 +345,8 @@
  *  3   Local   GPCM    8 bit  256MB  TEP2 (16 bit)
  */
 
-/*
- * Configuration for C2 on the local bus
- */
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_APP1_BASE | \
-                                BR_PS_8 | \
-                                BR_MS_GPCM | \
-                                BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | \
-                                OR_GPCM_CSNT | \
-                                OR_GPCM_ACS_DIV4 | \
-                                OR_GPCM_SCY_2 | \
-                                OR_GPCM_TRLX_SET | \
-                                OR_GPCM_EHTR_CLEAR | \
-                                OR_GPCM_EAD)
+/* APP1 */
+#define CONFIG_SYS_BR2_PRELIM  (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
 
 #endif /* __CONFIG_H */

diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
index 18476c12de29192e229481bc87a930ff6e39ab5d..1bff837198038a92bf1e1dd00fcf3bb2d1db68ac 100644 (file)
--- a/include/configs/tuxx1.h
+++ b/include/configs/tuxx1.h
@@ -113,15 +113,9 @@
  */
 #define CONFIG_SYS_FLASH_SIZE          256 /* max FLASH size is 256M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | \
-                               BR_PS_16 | /* 16 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_5 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM  (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1   /* max num of flash banks   */
 #define CONFIG_SYS_MAX_FLASH_SECT      512 /* max num of sects on one chip */
@@ -130,15 +124,10 @@
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
-/* Window base at flash base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_KMBEC_FPGA_BASE | \
-                               BR_PS_8 | /* 8 bit port size */ \
-                               BR_MS_GPCM | /* MSEL = GPCM */ \
-                               BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | \
-                               OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
-                               OR_GPCM_SCY_2 | \
-                               OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+
+/* KMBEC_FPGA */
+#define CONFIG_SYS_BR1_PRELIM  (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -358,36 +347,13 @@
  *  3   Local   GPCM    8 bit  256MB  TEP2 (16 bit)
  */
 
-/*
- * Configuration for C2 on the local bus
- */
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_APP1_BASE | \
-                                BR_PS_8 | \
-                                BR_MS_GPCM | \
-                                BR_V)
-
-#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | \
-                                OR_GPCM_CSNT | \
-                                OR_GPCM_ACS_DIV4 | \
-                                OR_GPCM_SCY_2 | \
-                                OR_GPCM_TRLX_SET | \
-                                OR_GPCM_EHTR_CLEAR | \
-                                OR_GPCM_EAD)
+/* APP1 */
+#define CONFIG_SYS_BR2_PRELIM  (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD)
 
-/*
- * Configuration for C3 on the local bus
- */
-#define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_APP2_BASE | \
-                                BR_PS_8 |              \
-                                BR_MS_GPCM |           \
-                                BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | \
-                                OR_GPCM_CSNT | \
-                                OR_GPCM_ACS_DIV2 | \
-                                OR_GPCM_SCY_2 | \
-                                OR_GPCM_TRLX_SET | \
-                                OR_GPCM_EHTR_CLEAR)
+/* APP2 */
+#define CONFIG_SYS_BR3_PRELIM  (0xB0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_SYS_MAMR                (MxMR_GPL_x4DIS | \
                                 0x0000c000 | \

diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 7dcc150f1955960fbd1a94c4599a30337aa9db60..3a5bcf9c62f28ea66815e2cba9736a830f8ae9d7 100644 (file)
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -153,63 +153,25 @@
 #define CONFIG_NAND_FSL_ELBC 1
 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
-                                       | BR_PS_16      /* 16 bit */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_ACS_DIV4 \
-                                       | OR_GPCM_SCY_5 \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xfe000c55 */
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
-                                       | BR_PS_8               \
-                                       | BR_DECC_CHK_GEN       \
-                                       | BR_MS_FCM             \
-                                       | BR_V) /* valid */
-                                       /* 0x61000c21 */
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
-                                       | OR_FCM_BCTLD \
-                                       | OR_FCM_CHT \
-                                       | OR_FCM_SCY_2 \
-                                       | OR_FCM_RST \
-                                       | OR_FCM_TRLX) /* 0xffff90ac */
+/* NAND */
+#define CONFIG_SYS_BR1_PRELIM (0x61000000 | BR_PS_8 | BR_DECC_CHK_GEN | BR_MS_FCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CHT | OR_FCM_SCY_2 | OR_FCM_RST | OR_FCM_TRLX)
 
 /* Still needed for spl_minimal.c */
 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 
-/* CS2 NvRAM */
-#define CONFIG_SYS_BR2_PRELIM  (0x60000000 \
-                               | BR_PS_8 \
-                               | BR_V)
-                               /* 0x60000801 */
-#define CONFIG_SYS_OR2_PRELIM  (OR_AM_128KB \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_3 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xfffe0937 */
-/* local bus read write buffer mapping SRAM@0x64000000 */
-#define CONFIG_SYS_BR3_PRELIM  (0x62000000 \
-                               | BR_PS_16 \
-                               | BR_V)
-                               /* 0x62001001 */
-
-#define CONFIG_SYS_OR3_PRELIM  (OR_AM_32MB \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xfe0009f7 */
+/* NVRAM */
+#define CONFIG_SYS_BR2_PRELIM  (0x60000000 | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
+
+/* SRAM */
+#define CONFIG_SYS_BR3_PRELIM  (0x62000000 | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port

diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 76821e7a407a74194a7e09e59868fc5997f293a3..dd8aae511730a16df0166cfaaeca90540584b431 100644 (file)
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -69,31 +69,16 @@
  */
 #define CONFIG_SYS_FLASH_BASE          0xf8000000      /* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE          128             /* flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM          (CONFIG_SYS_FLASH_BASE | \
-                                        BR_PS_16 |     /*  16bit */ \
-                                        BR_MS_GPCM |   /*  MSEL = GPCM */ \
-                                        BR_V)          /* valid */
-
-#define CONFIG_SYS_OR0_PRELIM          (OR_AM_128MB \
-                                       | OR_GPCM_XAM \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_ACS_DIV2 \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xf8006ff7 */
+
+/* FLASH */
+#define CONFIG_SYS_BR0_PRELIM          (0xF8000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM          (OR_AM_128MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_WINDOW1_BASE                0xf0000000
-#define CONFIG_SYS_BR1_PRELIM          (CONFIG_SYS_WINDOW1_BASE \
-                                       | BR_PS_32 \
-                                       | BR_MS_GPCM \
-                                       | BR_V)
-                                       /* 0xF0001801 */
-#define CONFIG_SYS_OR1_PRELIM          (OR_AM_256KB \
-                                       | OR_GPCM_SETA)
-                                       /* 0xfffc0208 */
+
+/* WINDOW1 */
+#define CONFIG_SYS_BR1_PRELIM          (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM          (OR_AM_256KB | OR_GPCM_SETA)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device*/