arm: mvebu: Move PCI(e) MBUS window to end of RAM

With patch 49b23e035d96 (pci: mvebu: Increase size of PCIe default mapping)
the mapping size for each PCI(e) controller was increased from 32MiB to
128MiB. This leads to problems on boards with multiple PCIe slots / ports
which are unable to map all PCIe ports, e.g. the Armada-XP theadorable:

DRAM:  2 GiB (667 MHz, 64-bit, ECC not enabled)
SF: Detected m25p128 with page size 256 Bytes, erase size 256 KiB, total 16 MiB
Cannot add window '4:f8', conflicts with another window
PCIe unable to add mbus window for mem at f0000000+08000000
Model: Marvell Armada XP theadorable

This patch moves the base address for the PCI(e) memory spaces from
0xe8000000 to the end of SDRAM (clipped to a max of 0xc0000000 right now).
This gives move room and flexibility for PCI(e) mappings.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: VlaoMao <vlaomao@gmail.com>
Tested-by: VlaoMao <vlaomao at gmail.com>

diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c
index 68383d06a274d516f196c8faaba91b837242d3df..fa8c799a462e0c3f0c513bc5b7598973f8b5e6ab 100644 (file)
--- a/arch/arm/mach-mvebu/dram.c
+++ b/arch/arm/mach-mvebu/dram.c
@@ -33,7 +33,9 @@ struct sdram_addr_dec {
 #define REG_CPUCS_WIN_WIN0_CS(x)       (((x) & 0x3) << 2)
 #define REG_CPUCS_WIN_SIZE(x)          (((x) & 0xff) << 24)
 
-#define SDRAM_SIZE_MAX                 0xc0000000
+#ifndef MVEBU_SDRAM_SIZE_MAX
+#define MVEBU_SDRAM_SIZE_MAX           0xc0000000
+#endif
 
 #define SCRUB_MAGIC            0xbeefdead
 
@@ -275,8 +277,8 @@ int dram_init(void)
                 * address space left for the internal registers etc.
                 */
                size += mvebu_sdram_bs(i);
-               if (size > SDRAM_SIZE_MAX)
-                       size = SDRAM_SIZE_MAX;
+               if (size > MVEBU_SDRAM_SIZE_MAX)
+                       size = MVEBU_SDRAM_SIZE_MAX;
        }
 
        for (; i < CONFIG_NR_DRAM_BANKS; i++) {
@@ -312,7 +314,7 @@ int dram_init_banksize(void)
 
                /* Clip the banksize to 1GiB if it exceeds the max size */
                size += gd->bd->bi_dram[i].size;
-               if (size > SDRAM_SIZE_MAX)
+               if (size > MVEBU_SDRAM_SIZE_MAX)
                        mvebu_sdram_bs_set(i, 0x40000000);
        }
 

diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index d1042100a82b87f8411bb7439c11ae758501c7a7..85d7dd1610a8ceabaf2239133ccc7f7a1c908903 100644 (file)
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -68,10 +68,12 @@ enum {
        MVEBU_SOC_UNKNOWN,
 };
 
+#define MVEBU_SDRAM_SIZE_MAX   0xc0000000
+
 /*
  * Default Device Address MAP BAR values
  */
-#define MBUS_PCI_MEM_BASE      0xE8000000
+#define MBUS_PCI_MEM_BASE      MVEBU_SDRAM_SIZE_MAX
 #define MBUS_PCI_MEM_SIZE      (128 << 20)
 #define MBUS_PCI_IO_BASE       0xF1100000
 #define MBUS_PCI_IO_SIZE       (64 << 10)