ARM: zynq: Add DTSes for mini qspi configurations

Mini U-Boot is running out of OCM and it's only purpose is to program non
volatile memories. There are different configurations which qspi can be
that's why describe them via DT.
DT binding is already approved that's why there is no reason not to add it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e7d31a9d9c4a76e171eefc619f31fabd0831a614.1698329087.git.michal.simek@amd.com

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c7e03c5364329398e0a777f42f90d175d8c71436..e7c8637df52a9b54c6a638a98ed02324dd42cdc4 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -423,6 +423,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
        zynqmp-mini-emmc1.dtb                   \
        zynqmp-mini-nand.dtb                    \
        zynqmp-mini-qspi.dtb                    \
+       zynqmp-mini-qspi-parallel.dtb           \
+       zynqmp-mini-qspi-single.dtb             \
+       zynqmp-mini-qspi-stacked.dtb            \
+       zynqmp-mini-qspi-x1-single.dtb          \
+       zynqmp-mini-qspi-x1-stacked.dtb         \
+       zynqmp-mini-qspi-x2-single.dtb          \
+       zynqmp-mini-qspi-x2-stacked.dtb         \
        zynqmp-sc-revB.dtb                      \
        zynqmp-sc-revC.dtb                      \
        zynqmp-sc-vek280-revA.dtbo              \

diff --git a/arch/arm/dts/zynqmp-mini-qspi-parallel.dts b/arch/arm/dts/zynqmp-mini-qspi-parallel.dts
new file mode 100644 (file)
index 0000000..728e822
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-parallel.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI Quad Parallel DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+       model = "ZynqMP MINI QSPI PARALLEL";
+};
+
+&qspi {
+       num-cs = <2>;
+};
+
+&flash0 {
+       reg = <0>, <1>;
+       parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+};

diff --git a/arch/arm/dts/zynqmp-mini-qspi-single.dts b/arch/arm/dts/zynqmp-mini-qspi-single.dts
new file mode 100644 (file)
index 0000000..0f9306e
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-single.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+       model = "ZynqMP MINI QSPI SINGLE";
+};

diff --git a/arch/arm/dts/zynqmp-mini-qspi-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-stacked.dts
new file mode 100644 (file)
index 0000000..9a9541b
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-stacked.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+       model = "ZynqMP MINI QSPI STACKED";
+};
+
+&qspi {
+       num-cs = <2>;
+};
+
+&flash0 {
+       reg = <0>, <1>;
+       stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+};

diff --git a/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts b/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts
new file mode 100644 (file)
index 0000000..5af875c
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI x1 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+       model = "ZynqMP MINI QSPI X1 SINGLE";
+};
+
+&flash0 {
+       spi-tx-bus-width = <1>;
+       spi-rx-bus-width = <1>;
+};

diff --git a/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts
new file mode 100644 (file)
index 0000000..ebf890e
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI x1 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+       model = "ZynqMP MINI QSPI X1 STACKED";
+};
+
+&qspi {
+       num-cs = <2>;
+};
+
+&flash0 {
+       reg = <0>, <1>;
+       stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+       spi-tx-bus-width = <1>;
+       spi-rx-bus-width = <1>;
+};

diff --git a/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts b/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts
new file mode 100644 (file)
index 0000000..a5ab315
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x2 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+       model = "ZynqMP MINI QSPI X2 SINGLE";
+};
+
+&flash0 {
+       spi-tx-bus-width = <2>;
+       spi-rx-bus-width = <2>;
+};

diff --git a/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts
new file mode 100644 (file)
index 0000000..e234b76
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI x2 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+       model = "ZynqMP MINI QSPI X2 STACKED";
+};
+
+&qspi {
+       num-cs = <2>;
+};
+
+&flash0 {
+       reg = <0>, <1>;
+       stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+       spi-tx-bus-width = <2>;
+       spi-rx-bus-width = <2>;
+};