config: arm: exynos5250: Define CONFIG_SYS_CACHELINE_SIZE

XHCI stack driver needs this to align buffers to
CacheLine boundary. So define the same to be '64'

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>

diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 8c21909d634f600f64f9c0376ea8819cc272f5e6..c9c19a75f3352d85e02a42ffb3c7713fa12c0565 100644 (file)
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -37,6 +37,8 @@
 /* Keep L2 Cache Disabled */
 #define CONFIG_SYS_DCACHE_OFF
 
+#define CONFIG_SYS_CACHELINE_SIZE      64
+
 /* Enable ACE acceleration for SHA1 and SHA256 */
 #define CONFIG_EXYNOS_ACE_SHA
 #define CONFIG_SHA_HW_ACCEL