]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
msc_sm2s_imx8mp: Convert to DM_SERIAL
authorFabio Estevam <festevam@denx.de>
Tue, 13 Feb 2024 11:43:38 +0000 (08:43 -0300)
committerFabio Estevam <festevam@denx.de>
Mon, 19 Feb 2024 11:19:39 +0000 (08:19 -0300)
The conversion to DM_SERIAL is mandatory, so do the conversion.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Ian Ray <ian.ray@gehealthcare.com>
arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
board/msc/sm2s_imx8mp/spl.c
configs/msc_sm2s_imx8mp_defconfig
include/configs/msc_sm2s_imx8mp.h

index c398a743f7b02cd1b0db55a59ab3bce98d778ce5..1a7b530d9fc9496fc536b30ce94a09a7ebed1d4c 100644 (file)
 &pmic {
        bootph-pre-ram;
 };
+
+&uart2 {
+       bootph-pre-ram;
+};
+
+&pinctrl_uart2 {
+       bootph-pre-ram;
+};
index fed0fbcba1e4ef0ac5613e6a6557e92f00c7d5c6..ed7a1b7d3d00269e31c31290c1ed6900f9313d82 100644 (file)
@@ -168,13 +168,6 @@ static const iomux_v3_cfg_t wdog_pads[] = {
        MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
 
-#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-
-static const iomux_v3_cfg_t ser0_pads[] = {
-       MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-       MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 int board_early_init_f(void)
 {
        struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
@@ -182,8 +175,6 @@ int board_early_init_f(void)
        imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
        set_wdog_reset(wdog);
 
-       imx_iomux_v3_setup_multiple_pads(ser0_pads, ARRAY_SIZE(ser0_pads));
-
        return 0;
 }
 
index bf1052db6f2d713b95bde67ebef56ef310aff6f5..9c27a72f8a0fb1d25a2a3ebc1c206782b6730dda 100644 (file)
@@ -97,6 +97,7 @@ CONFIG_SPL_PMIC_RN5T567=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
index c1c1fd5a78434cfb24ef0ea3cfb28d043016049f..3c7d96cb3c0aeefda91c87af63c4f2f609291f1c 100644 (file)
@@ -55,8 +55,6 @@
 #define PHYS_SDRAM_2                   0xc0000000
 #define PHYS_SDRAM_2_SIZE              0x0
 
-#define CFG_MXC_UART_BASE              UART2_BASE_ADDR
-
 #define CFG_SYS_FSL_USDHC_NUM  2
 #define CFG_SYS_FSL_ESDHC_ADDR 0