bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
-config TARGET_SOCFPGA_DENX_MCVEVK
- bool "DENX MCVEVK (Cyclone V)"
+config TARGET_SOCFPGA_ARIES_MCVEVK
+ bool "Aries MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_EBV_SOCRATES
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "is1" if TARGET_SOCFPGA_IS1
- default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+ default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
- default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+ default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_is1" if TARGET_SOCFPGA_IS1
- default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+ default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __CONFIG_DENX_MCVEVK_H__
-#define __CONFIG_DENX_MCVEVK_H__
+#ifndef __CONFIG_ARIES_MCVEVK_H__
+#define __CONFIG_ARIES_MCVEVK_H__
#include <asm/arch/base_addr_ac5.h>
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
-#endif /* __CONFIG_DENX_MCVEVK_H__ */
+#endif /* __CONFIG_ARIES_MCVEVK_H__ */