]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
ARM: socfpga: Rename MCVEVK
authorMarek Vasut <marex@denx.de>
Wed, 5 Apr 2017 11:17:03 +0000 (13:17 +0200)
committerMarek Vasut <marex@denx.de>
Fri, 14 Apr 2017 12:06:44 +0000 (14:06 +0200)
The board is now manufactured by Aries Embedded GmbH , rename it.

Signed-off-by: Marek Vasut <marex@denx.de>
arch/arm/dts/socfpga_cyclone5_mcvevk.dts
arch/arm/mach-socfpga/Kconfig
board/aries/mcvevk/MAINTAINERS [moved from board/denx/mcvevk/MAINTAINERS with 59% similarity]
board/aries/mcvevk/Makefile [moved from board/denx/mcvevk/Makefile with 100% similarity]
board/aries/mcvevk/qts/iocsr_config.h [moved from board/denx/mcvevk/qts/iocsr_config.h with 100% similarity]
board/aries/mcvevk/qts/pinmux_config.h [moved from board/denx/mcvevk/qts/pinmux_config.h with 100% similarity]
board/aries/mcvevk/qts/pll_config.h [moved from board/denx/mcvevk/qts/pll_config.h with 100% similarity]
board/aries/mcvevk/qts/sdram_config.h [moved from board/denx/mcvevk/qts/sdram_config.h with 100% similarity]
board/aries/mcvevk/socfpga.c [moved from board/denx/mcvevk/socfpga.c with 100% similarity]
configs/socfpga_mcvevk_defconfig
include/configs/socfpga_mcvevk.h

index 7d3f9894723969a16e2b04a26107f16546fd3fcc..1462f0881ae5b3c4d281d7183d44517544e4fc66 100644 (file)
@@ -7,7 +7,7 @@
 #include "socfpga_cyclone5.dtsi"
 
 / {
-       model = "DENX MCVEVK";
+       model = "Aries MCVEVK";
        compatible = "altr,socfpga-cyclone5", "altr,socfpga";
 
        chosen {
index e56b3db1158987ecacca8ab9a9d239bc621311e2..18bb6dce3c86c18d6dfcb68c70968b13f184bb09 100644 (file)
@@ -56,8 +56,8 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
        bool "Altera SOCFPGA SoCDK (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
-config TARGET_SOCFPGA_DENX_MCVEVK
-       bool "DENX MCVEVK (Cyclone V)"
+config TARGET_SOCFPGA_ARIES_MCVEVK
+       bool "Aries MCVEVK (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_EBV_SOCRATES
@@ -97,7 +97,7 @@ config SYS_BOARD
        default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
        default "is1" if TARGET_SOCFPGA_IS1
-       default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+       default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
        default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "sr1500" if TARGET_SOCFPGA_SR1500
@@ -106,7 +106,7 @@ config SYS_BOARD
 config SYS_VENDOR
        default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
-       default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+       default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
        default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -122,7 +122,7 @@ config SYS_CONFIG_NAME
        default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
        default "socfpga_is1" if TARGET_SOCFPGA_IS1
-       default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+       default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
        default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
similarity index 59%
rename from board/denx/mcvevk/MAINTAINERS
rename to board/aries/mcvevk/MAINTAINERS
index 6787727d84cb638f6713717c72ae4e320b6fcf2e..c3a3a2b87dad9cfd154973429516e20a2cb38bef 100644 (file)
@@ -1,5 +1,5 @@
-SOCKIT BOARD
-M:     Marek Vasut <marex@denx.de>
+Aries MCVEVK BOARD
+M:     Marek Vasut <marek.vasut@gmail.com>
 S:     Maintained
 F:     include/configs/socfpga_mcvevk.h
 F:     configs/socfpga_mcvevk_defconfig
index b16ee1c06ab2b61e325c9b1f00be091d13ea21f0..627b90f7718e92617ce21baed94aaf249e80fc7b 100644 (file)
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y
+CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
 CONFIG_FIT=y
index 3c9ba6de23f4db2a6a29c4053487f5d4d270dfb7..604ea20e2cf42372e7c4782a5c1eb9e803e02391 100644 (file)
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
-#ifndef __CONFIG_DENX_MCVEVK_H__
-#define __CONFIG_DENX_MCVEVK_H__
+#ifndef __CONFIG_ARIES_MCVEVK_H__
+#define __CONFIG_ARIES_MCVEVK_H__
 
 #include <asm/arch/base_addr_ac5.h>
 
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
 
-#endif /* __CONFIG_DENX_MCVEVK_H__ */
+#endif /* __CONFIG_ARIES_MCVEVK_H__ */