#define CSR_OPS 0x0000000F
#define CSR_OPS_CONFIG BIT(1)
+#define APSR_RDM BIT(13)
#define APSR_TDM BIT(14)
#define TCCR_TSRQ0 BIT(0)
struct ravb_priv *eth = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
int ret = 0;
+ int mode = 0;
+ unsigned int delay;
+ bool explicit_delay = false;
/* Set CONFIG mode */
ret = ravb_reset(dev);
(rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
return 0;
- if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
- (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID))
- writel(APSR_TDM, eth->iobase + RAVB_REG_APSR);
+ if (!dev_read_u32(dev, "rx-internal-delay-ps", &delay)) {
+ /* Valid values are 0 and 1800, according to DT bindings */
+ if (delay) {
+ mode |= APSR_RDM;
+ explicit_delay = true;
+ }
+ }
+
+ if (!dev_read_u32(dev, "tx-internal-delay-ps", &delay)) {
+ /* Valid values are 0 and 2000, according to DT bindings */
+ if (delay) {
+ mode |= APSR_TDM;
+ explicit_delay = true;
+ }
+ }
+
+ if (!explicit_delay) {
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ mode |= APSR_RDM;
+
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ mode |= APSR_TDM;
+ }
+
+ writel(mode, eth->iobase + RAVB_REG_APSR);
return 0;
}