riscv: Add a SYSCON driver for Andestech's PLMT

The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 511768befc2d0595692e597a0290c4fd55bbc552..ae8ff7b765786841971eedfa06cb4257418e375d 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -118,6 +118,15 @@ config ANDES_PLIC
          The Andes PLIC block holds memory-mapped claim and pending registers
          associated with software interrupt.
 
+config ANDES_PLMT
+       bool
+       depends on RISCV_MMODE
+       select REGMAP
+       select SYSCON
+       help
+         The Andes PLMT block holds memory-mapped mtime register
+         associated with timer tick.
+
 config RISCV_RDTIME
        bool
        default y if RISCV_SMODE

diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index b86791094bbc004e3fc266a9a8ef86a63f6bdf22..dffcd45bf01393888509db20c1bea2021ede3a32 100644 (file)
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -21,6 +21,9 @@ struct arch_global_data {
 #ifdef CONFIG_ANDES_PLIC
        void __iomem *plic;     /* plic base address */
 #endif
+#ifdef CONFIG_ANDES_PLMT
+       void __iomem *plmt;     /* plmt base address */
+#endif
 #ifdef CONFIG_SMP
        struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif

diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index a0862082612df77d6cecaf33cc859c6be5cec883..26a008ca59948393674ef9b9843b588b16fb7d89 100644 (file)
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -13,6 +13,7 @@ enum {
        RISCV_NONE,
        RISCV_SYSCON_CLINT,     /* Core Local Interruptor (CLINT) */
        RISCV_SYSCON_PLIC,      /* Platform Level Interrupt Controller (PLIC) */
+       RISCV_SYSCON_PLMT,      /* Platform Level Machine Timer (PLMT) */
 };
 
 #endif /* _ASM_SYSCON_H */

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 1bf554bad59f4da23fb26a992901cbdcb09c6ec3..1c332db436a9db87de191e31c482a59e528d6dfa 100644 (file)
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -12,6 +12,7 @@ obj-y += cache.o
 obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
+obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
 obj-y  += interrupts.o
 obj-y  += reset.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o

diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
new file mode 100644 (file)
index 0000000..84f4607
--- /dev/null
+++ b/arch/riscv/lib/andes_plmt.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen <rick@andestech.com>
+ *
+ * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
+ * The PLMT block holds memory-mapped mtime register
+ * associated with timer tick.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+
+/* mtime register */
+#define MTIME_REG(base)                        ((ulong)(base))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLMT_BASE_GET(void)                                            \
+       do {                                                            \
+               long *ret;                                              \
+                                                                       \
+               if (!gd->arch.plmt) {                                   \
+                       ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
+                       if (IS_ERR(ret))                                \
+                               return PTR_ERR(ret);                    \
+                       gd->arch.plmt = ret;                            \
+               }                                                       \
+       } while (0)
+
+int riscv_get_time(u64 *time)
+{
+       PLMT_BASE_GET();
+
+       *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
+
+       return 0;
+}
+
+static const struct udevice_id andes_plmt_ids[] = {
+       { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
+       { }
+};
+
+U_BOOT_DRIVER(andes_plmt) = {
+       .name           = "andes_plmt",
+       .id             = UCLASS_SYSCON,
+       .of_match       = andes_plmt_ids,
+       .flags          = DM_FLAG_PRE_RELOC,
+};