bool "Support flea3"
select CPU_ARM1136
-config TARGET_MX35PDK
- bool "Support mx35pdk"
- select BOARD_LATE_INIT
- select CPU_ARM1136
-
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select DM
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
source "board/freescale/lx2160a/Kconfig"
-source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/hisilicon/hikey/Kconfig"
+++ /dev/null
-if TARGET_MX35PDK
-
-config SYS_BOARD
- default "mx35pdk"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "mx35"
-
-config SYS_CONFIG_NAME
- default "mx35pdk"
-
-endif
+++ /dev/null
-MX35PDK BOARD
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/freescale/mx35pdk/
-F: include/configs/mx35pdk.h
-F: configs/mx35pdk_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-
-obj-y := mx35pdk.o
-obj-y += lowlevel_init.o
+++ /dev/null
-Overview
---------------
-
-mx35pdk (known als as mx35_3stack) is a development board by Freescale.
-It consists of three pluggable board:
- - CPU module, with CPU, RAM, flash
- - Personality board, with most interfaces (USB, Network,..)
- - Debug board with JTAG header.
-
-The board is usually delivered with redboot. This howto explains how to boot
-a linux kernel and how to replace the original bootloader with U-Boot.
-
-The board is delivered with Redboot on the NAND flash. It is possible to
-switch the boot device with the switches SW1-SW2 on the Personality board,
-and with SW5-SW10 on the Debug board.
-
-Delivered Redboot script to start the kernel
----------------------------------------------------
-
-In redboot the following script is stored:
-
-fis load kernel
-exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76"
-
-Kernel is taken from flash. The image is in zImage format.
-
-Booting from NET, rootfs on NFS:
------------------------------------
-
-To change the script in redboot:
-
-load -r -b 0x100000 <path_to_zImage>
-exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp"
-
-If the ip address is not set, you can set it with :
-
-ip_address -l <board_ip/netmask> -h <server_ip>
-
-Linux partitions:
----------------------------
-
-As default, the board is shipped with these partition tables for NAND
-and for NOR:
-
-Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit":
-0x00000000-0x00100000 : "nand.bootloader"
-0x00100000-0x00600000 : "nand.kernel"
-0x00600000-0x06600000 : "nand.rootfs"
-0x06600000-0x06e00000 : "nand.configure"
-0x06e00000-0x80000000 : "nand.userfs"
-
-Creating 6 MTD partitions on "mxc_nor_flash.0":
-0x00000000-0x00080000 : "Bootloader"
-0x00080000-0x00480000 : "nor.Kernel"
-0x00480000-0x02280000 : "nor.userfs"
-0x02280000-0x03e80000 : "nor.rootfs"
-0x01fe0000-0x01fe3000 : "FIS directory"
-0x01fff000-0x04000000 : "Redboot config"
-
-NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS.
-For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2.
-
-However, the setup in redboot is not correct and does not use the whole flash.
-
-Better solution is to use the kernel parameter mtdparts.
-Here the resulting script to be defined in RedBoot with fconfig:
-
-load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37
-exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
-
-Flashing U-Boot
---------------------------------
-
-U-Boot should be stored on the NOR flash.
-
-The boot storage can be select using the switches on the personality board
-(SW1-SW2) and on the DEBUG board (SW4-SW10).
-
-If something goes wrong flashing the bootloader, it is always possible to
-recover the board booting from the other device.
-
-Saving U-Boot in the NOR flash
----------------------------------
-
-Check the partition for boot in the NOR flash. Setting the mtdparts as reported,
-the boot partition should be /dev/mtd0.
-
-Creating 6 MTD partitions on "mxc_nor_flash.0":
-0x00000000-0x00080000 : "Bootloader"
-0x00080000-0x00480000 : "nor.Kernel"
-0x00480000-0x02280000 : "nor.userfs"
-0x02280000-0x03e80000 : "nor.rootfs"
-0x01fe0000-0x01fe3000 : "FIS directory"
-0x01fff000-0x04000000 : "Redboot config"
-
-To erase the whole partition:
-$ flash_eraseall /dev/mtd0
-
-Writing U-Boot:
-dd if=u-boot.bin of=/dev/mtd0
-
-To boot from NOR, you have to select the switches as follows:
-
-Personality board
- SW2 all off
- SW1 all off
-
-Debug Board:
- SW5 0
- SW6 0
- SW7 0
- SW8 1
- SW9 1
- SW10 0
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-#include "mx35pdk.h"
-#include <asm/arch/lowlevel_macro.S>
-
-/*
- * return soc version
- * 0x10: TO1
- * 0x20: TO2
- * 0x30: TO3
- */
-.macro check_soc_version ret, tmp
- ldr \tmp, =IIM_BASE_ADDR
- ldr \ret, [\tmp, #IIM_SREV]
- cmp \ret, #0x00
- moveq \tmp, #ROMPATCH_REV
- ldreq \ret, [\tmp]
- moveq \ret, \ret, lsl #4
- addne \ret, \ret, #0x10
-.endm
-
-/* CPLD on CS5 setup */
-.macro init_debug_board
- ldr r0, =DBG_BASE_ADDR
- ldr r1, =DBG_CSCR_U_CONFIG
- str r1, [r0, #0x00]
- ldr r1, =DBG_CSCR_L_CONFIG
- str r1, [r0, #0x04]
- ldr r1, =DBG_CSCR_A_CONFIG
- str r1, [r0, #0x08]
-.endm
-
-/* clock setup */
-.macro init_clock
- ldr r0, =CCM_BASE_ADDR
-
- /* default CLKO to 1/32 of the ARM core*/
- ldr r1, [r0, #CLKCTL_COSR]
- bic r1, r1, #0x00000FF00
- bic r1, r1, #0x0000000FF
- mov r2, #0x00006C00
- add r2, r2, #0x67
- orr r1, r1, r2
- str r1, [r0, #CLKCTL_COSR]
-
- ldr r2, =CCM_CCMR_CONFIG
- str r2, [r0, #CLKCTL_CCMR]
-
- check_soc_version r1, r2
- cmp r1, #CHIP_REV_2_0
- ldrhs r3, =CCM_MPLL_532_HZ
- bhs 1f
- ldr r2, [r0, #CLKCTL_PDR0]
- tst r2, #CLKMODE_CONSUMER
- ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
- ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
-1:
- str r3, [r0, #CLKCTL_MPCTL]
-
- ldr r1, =CCM_PPLL_300_HZ
- str r1, [r0, #CLKCTL_PPCTL]
-
- ldr r1, =CCM_PDR0_CONFIG
- bic r1, r1, #0x800000
- str r1, [r0, #CLKCTL_PDR0]
-
- ldr r1, [r0, #CLKCTL_CGR0]
- orr r1, r1, #0x0C300000
- str r1, [r0, #CLKCTL_CGR0]
-
- ldr r1, [r0, #CLKCTL_CGR1]
- orr r1, r1, #0x00000C00
- orr r1, r1, #0x00000003
- str r1, [r0, #CLKCTL_CGR1]
-
- ldr r1, [r0, #CLKCTL_CGR2]
- orr r1, r1, #0x00C00000
- str r1, [r0, #CLKCTL_CGR2]
-.endm
-
-.macro setup_sdram
- ldr r0, =ESDCTL_BASE_ADDR
- mov r3, #0x2000
- str r3, [r0, #0x0]
- str r3, [r0, #0x8]
-
- /*ip(r12) has used to save lr register in upper calling*/
- mov fp, lr
-
- mov r5, #0x00
- mov r2, #0x00
- mov r1, #CSD0_BASE_ADDR
- bl setup_sdram_bank
-
- mov r5, #0x00
- mov r2, #0x00
- mov r1, #CSD1_BASE_ADDR
- bl setup_sdram_bank
-
- mov lr, fp
-
-1:
- ldr r3, =ESDCTL_DELAY_LINE5
- str r3, [r0, #0x30]
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
- mov r10, lr
-
- core_init
-
- init_aips
-
- init_max
-
- init_m3if
-
- init_clock
- init_debug_board
-
- cmp pc, #PHYS_SDRAM_1
- blo init_sdram_start
- cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
- blo skip_sdram_setup
-
-init_sdram_start:
- /*init_sdram*/
- setup_sdram
-
-skip_sdram_setup:
- mov lr, r10
- mov pc, lr
-
-
-/*
- * r0: ESDCTL control base, r1: sdram slot base
- * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
- */
-setup_sdram_bank:
- mov r3, #0xE
- tst r2, #0x1
- orreq r3, r3, #0x300 /*DDR2*/
- str r3, [r0, #0x10]
- bic r3, r3, #0x00A
- str r3, [r0, #0x10]
- beq 2f
-
- mov r3, #0x20000
-1: subs r3, r3, #1
- bne 1b
-
-2: tst r2, #0x1
- ldreq r3, =ESDCTL_DDR2_CONFIG
- ldrne r3, =ESDCTL_MDDR_CONFIG
- cmp r1, #CSD1_BASE_ADDR
- strlo r3, [r0, #0x4]
- strhs r3, [r0, #0xC]
-
- ldr r3, =ESDCTL_0x92220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_PRECHARGE
- strb r3, [r1, r4]
-
- tst r2, #0x1
- bne skip_set_mode
-
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0xB2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_DDR2_EMR2
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_EMR3
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_EN_DLL
- strb r3, [r1, r4]
- ldr r4, =ESDCTL_DDR2_RESET_DLL
- strb r3, [r1, r4]
-
- ldr r3, =ESDCTL_0x92220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- ldr r4, =ESDCTL_PRECHARGE
- strb r3, [r1, r4]
-
-skip_set_mode:
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0xA2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- mov r3, #0xDA
- strb r3, [r1]
- strb r3, [r1]
-
- ldr r3, =ESDCTL_0xB2220000
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
- tst r2, #0x1
- ldreq r4, =ESDCTL_DDR2_MR
- ldrne r4, =ESDCTL_MDDR_MR
- mov r3, #0xDA
- strb r3, [r1, r4]
- ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
- streqb r3, [r1, r4]
- ldreq r4, =ESDCTL_DDR2_EN_DLL
- ldrne r4, =ESDCTL_MDDR_EMR
- strb r3, [r1, r4]
-
- cmp r1, #CSD1_BASE_ADDR
- ldr r3, =ESDCTL_0x82228080
- strlo r3, [r0, #0x0]
- strhs r3, [r0, #0x8]
-
- tst r2, #0x1
- moveq r4, #0x20000
- movne r4, #0x200
-1: subs r4, r4, #1
- bne 1b
-
- str r3, [r1, #0x100]
- ldr r4, [r1, #0x100]
- cmp r3, r4
- movne r3, #1
- moveq r3, #0
-
- mov pc, lr
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx35.h>
-#include <i2c.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <mc9sdz60.h>
-#include <mc13892.h>
-#include <linux/types.h>
-#include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <netdev.h>
-#include <asm/mach-types.h>
-
-#ifndef CONFIG_BOARD_LATE_INIT
-#error "CONFIG_BOARD_LATE_INIT must be set for this board"
-#endif
-
-#ifndef CONFIG_BOARD_EARLY_INIT_F
-#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- u32 size1, size2;
-
- size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
-
- gd->ram_size = size1 + size2;
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-
- return 0;
-}
-
-#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
-
-static void setup_iomux_i2c(void)
-{
- static const iomux_v3_cfg_t i2c1_pads[] = {
- NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
- };
-
- /* setup pins for I2C1 */
- imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
-}
-
-
-static void setup_iomux_spi(void)
-{
- static const iomux_v3_cfg_t spi_pads[] = {
- MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
- MX35_PAD_CSPI1_MISO__CSPI1_MISO,
- MX35_PAD_CSPI1_SS0__CSPI1_SS0,
- MX35_PAD_CSPI1_SS1__CSPI1_SS1,
- MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
- };
-
- imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
-}
-
-#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
- PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
-#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
-
-static void setup_iomux_usbotg(void)
-{
- static const iomux_v3_cfg_t usbotg_pads[] = {
- NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
- USBOTG_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
- USBOTG_IN_PAD_CTRL),
- };
-
- /* Set up pins for USBOTG. */
- imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
-}
-
-#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
-
-static void setup_iomux_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
- NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
- NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
- NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
- };
-
- /* setup pins for FEC */
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-int board_early_init_f(void)
-{
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
-
- /* enable clocks */
- writel(readl(&ccm->cgr0) |
- MXC_CCM_CGR0_EMI_MASK |
- MXC_CCM_CGR0_EDIO_MASK |
- MXC_CCM_CGR0_EPIT1_MASK,
- &ccm->cgr0);
-
- writel(readl(&ccm->cgr1) |
- MXC_CCM_CGR1_FEC_MASK |
- MXC_CCM_CGR1_GPIO1_MASK |
- MXC_CCM_CGR1_GPIO2_MASK |
- MXC_CCM_CGR1_GPIO3_MASK |
- MXC_CCM_CGR1_I2C1_MASK |
- MXC_CCM_CGR1_I2C2_MASK |
- MXC_CCM_CGR1_IPU_MASK,
- &ccm->cgr1);
-
- /* Setup NAND */
- __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
-
- setup_iomux_i2c();
- setup_iomux_usbotg();
- setup_iomux_fec();
- setup_iomux_spi();
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-static inline int pmic_detect(void)
-{
- unsigned int id;
- struct pmic *p = pmic_get("FSL_PMIC");
- if (!p)
- return -ENODEV;
-
- pmic_reg_read(p, REG_IDENTIFICATION, &id);
-
- id = (id >> 6) & 0x7;
- if (id == 0x7)
- return 1;
- return 0;
-}
-
-u32 get_board_rev(void)
-{
- int rev;
-
- rev = pmic_detect();
-
- return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
-}
-
-int board_late_init(void)
-{
- u8 val;
- u32 pmic_val;
- struct pmic *p;
- int ret;
-
- ret = pmic_init(I2C_0);
- if (ret)
- return ret;
-
- if (pmic_detect()) {
- p = pmic_get("FSL_PMIC");
- imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
-
- pmic_reg_read(p, REG_SETTING_0, &pmic_val);
- pmic_reg_write(p, REG_SETTING_0,
- pmic_val | VO_1_30V | VO_1_50V);
- pmic_reg_read(p, REG_MODE_0, &pmic_val);
- pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
-
- imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
-
- gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
- }
-
- val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
- mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
- mdelay(200);
-
- val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
- mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
- mdelay(200);
-
- val |= 0x80;
- mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
-
- /* Print board revision */
- printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_SMC911X)
- int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
- if (rc)
- return rc;
-#endif
- return cpu_eth_init(bis);
-}
-
-#if defined(CONFIG_FSL_ESDHC_IMX)
-
-struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
-
-int board_mmc_init(struct bd_info *bis)
-{
- static const iomux_v3_cfg_t sdhc1_pads[] = {
- MX35_PAD_SD1_CMD__ESDHC1_CMD,
- MX35_PAD_SD1_CLK__ESDHC1_CLK,
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
- };
-
- /* configure pins for SDHC1 only */
- imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
-
- esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
- return fsl_esdhc_initialize(bis, &esdhc_cfg);
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
-}
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- */
-
-#ifndef __BOARD_MX35_3STACK_H
-#define __BOARD_MX35_3STACK_H
-
-#define DBG_BASE_ADDR WEIM_CTRL_CS5
-#define DBG_CSCR_U_CONFIG 0x0000D843
-#define DBG_CSCR_L_CONFIG 0x22252521
-#define DBG_CSCR_A_CONFIG 0x22220A00
-
-#define CCM_CCMR_CONFIG 0x003F4208
-#define CCM_PDR0_CONFIG 0x00801000
-
-/* MEMORY SETTING */
-#define ESDCTL_0x92220000 0x92220000
-#define ESDCTL_0xA2220000 0xA2220000
-#define ESDCTL_0xB2220000 0xB2220000
-#define ESDCTL_0x82228080 0x82228080
-
-#define ESDCTL_PRECHARGE 0x00000400
-
-#define ESDCTL_MDDR_CONFIG 0x007FFC3F
-#define ESDCTL_MDDR_MR 0x00000033
-#define ESDCTL_MDDR_EMR 0x02000000
-
-#define ESDCTL_DDR2_CONFIG 0x007FFC3F
-#define ESDCTL_DDR2_EMR2 0x04000000
-#define ESDCTL_DDR2_EMR3 0x06000000
-#define ESDCTL_DDR2_EN_DLL 0x02000400
-#define ESDCTL_DDR2_RESET_DLL 0x00000333
-#define ESDCTL_DDR2_MR 0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-
-#define ESDCTL_DELAY_LINE5 0x00F49F00
-#endif /* __BOARD_MX35_3STACK_H */
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_TARGET_MX35PDK=y
-CONFIG_SYS_TEXT_BASE=0xA0000000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xA0080000
-CONFIG_ENV_ADDR_REDUND=0xA00A0000
-CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC_IMX=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXC=y
-CONFIG_MII=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0xB6000000
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
config MXC_UART
bool "IMX serial port support"
- depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 || TARGET_MX35PDK \
+ depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 \
|| MX5 || MX6 || MX7 || IMX8M
help
If you have a machine based on a Motorola IMX CPU you
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * Configuration for the MX35pdk Freescale board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
- /* High Level Configuration Options */
-#define CONFIG_MX35
-
-#define CONFIG_SYS_FSL_CLK
-
-/* Set TEXT at the beginning of the NOR flash */
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_REVISION_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
-/*
- * PMIC Configs
- */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_FSL
-#define CONFIG_POWER_FSL_MC13892
-#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
-#define CONFIG_RTC_MC13XXX
-
-/*
- * MFD MC9SDZ60
- */
-#define CONFIG_FSL_MC9SDZ60
-#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69
-
-/*
- * UART (console)
- */
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/*
- * Command definition
- */
-
-#define CONFIG_NET_RETRY_COUNT 100
-
-
-#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-
-/*
- * Ethernet on the debug board (SMC911)
- */
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETHPRIME
-
-/*
- * Ethernet on SOC (FEC)
- */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1F
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/*
- * Physical Memory Map
- */
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
-#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*
- * MTD Command for mtdparts
- */
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-/* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
-/* Address and size of Redundant Environment Sector */
-
-/*
- * CFI FLASH driver setup
- */
-
-/* A non-standard buffered write algorithm */
-#define CONFIG_FLASH_SPANSION_S29WS_N
-
-/*
- * NAND FLASH driver setup
- */
-#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-
-/* EHCI driver */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_MXC
-#define CONFIG_MXC_USB_PORT 0
-#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \
- MXC_EHCI_POWER_PINS_ENABLED | \
- MXC_EHCI_OC_PIN_ACTIVE_LOW)
-#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
-
-/* mmc driver */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-/*
- * Default environment and default scripts
- * to update uboot and load kernel
- */
-
-#define CONFIG_HOSTNAME "mx35pdk"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth1\0" \
- "ethprime=smc911x\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip_sta=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
- "addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=ttymxc0,${baudrate}\0" \
- "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
- "loadaddr=80800000\0" \
- "kernel_addr_r=80800000\0" \
- "hostname=" CONFIG_HOSTNAME "\0" \
- "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
- "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r}\0" \
- "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
- "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
- "update=protect off ${uboot_addr} +80000;" \
- "erase ${uboot_addr} +80000;" \
- "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
- "upd=if run load;then echo Updating u-boot;if run update;" \
- "then echo U-Boot updated;" \
- "else echo Error updating u-boot !;" \
- "echo Board without bootloader !!;" \
- "fi;" \
- "else echo U-Boot not downloaded..exiting;fi\0" \
- "bootcmd=run net_nfs\0"
-
-#endif /* __CONFIG_H */
projects / u-boot.git / commitdiff
