]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
drivers: use dev_read_addr_ptr when cast to pointer
authorJohan Jonker <jbx6244@gmail.com>
Mon, 13 Mar 2023 00:32:04 +0000 (01:32 +0100)
committerKever Yang <kever.yang@rock-chips.com>
Sat, 6 May 2023 09:28:18 +0000 (17:28 +0800)
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
47 files changed:
arch/arm/mach-mvebu/system-controller.c
doc/develop/driver-model/livetree.rst
drivers/ata/dwc_ahsata.c
drivers/cache/cache-l2x0.c
drivers/cache/cache-v5l2.c
drivers/gpio/mscc_sgpio.c
drivers/gpio/tegra_gpio.c
drivers/gpio/xilinx_gpio.c
drivers/i2c/i2c-cdns.c
drivers/i2c/tegra_i2c.c
drivers/mmc/am654_sdhci.c
drivers/mmc/davinci_mmc.c
drivers/mmc/piton_mmc.c
drivers/mmc/tegra_mmc.c
drivers/mmc/zynq_sdhci.c
drivers/mtd/nand/raw/arasan_nfc.c
drivers/mtd/nand/raw/cortina_nand.c
drivers/mtd/nand/raw/mxic_nand.c
drivers/mtd/nand/raw/tegra_nand.c
drivers/mtd/nand/raw/zynq_nand.c
drivers/net/mvmdio.c
drivers/net/qe/dm_qe_uec_phy.c
drivers/pci/pci-aardvark.c
drivers/phy/allwinner/phy-sun50i-usb3.c
drivers/phy/qcom/phy-qcom-usb-hs-28nm.c
drivers/phy/qcom/phy-qcom-usb-ss.c
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
drivers/phy/rockchip/phy-rockchip-typec.c
drivers/pwm/tegra_pwm.c
drivers/serial/serial_zynq.c
drivers/spi/mpc8xxx_spi.c
drivers/spi/mscc_bb_spi.c
drivers/spi/sh_qspi.c
drivers/spi/spi-mxic.c
drivers/spi/xilinx_spi.c
drivers/ufs/ufs.c
drivers/usb/host/ehci-tegra.c
drivers/video/dw_mipi_dsi.c
drivers/video/rockchip/rk_vop.c
drivers/video/stm32/stm32_dsi.c
drivers/video/stm32/stm32_ltdc.c
drivers/video/tegra124/display.c
drivers/video/tegra124/sor.c
drivers/video/ti/tilcdc.c
drivers/watchdog/cdns_wdt.c
drivers/watchdog/sp805_wdt.c
drivers/watchdog/xilinx_tb_wdt.c

index e90aff0c3379856078deae78be964dcd99f8692b..7cdde11cbd2ceebbf4f7d6359d592a63213a373d 100644 (file)
@@ -71,8 +71,8 @@ static int mvebu_reset_of_to_plat(struct udevice *dev)
 {
        struct mvebu_reset_data *data = dev_get_priv(dev);
 
-       data->base = (void *)dev_read_addr(dev);
-       if ((fdt_addr_t)data->base == FDT_ADDR_T_NONE)
+       data->base = dev_read_addr_ptr(dev);
+       if (!data->base)
                return -EINVAL;
 
        return 0;
index 579eef5ca9fe6fe904f8545708d4bd7e989a1a1b..20055d559a6f9266ec3fc50fb9142719e06974f1 100644 (file)
@@ -103,7 +103,7 @@ The new code is:
 
     struct udevice *bus;
 
-    i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
+    i2c_bus->regs = dev_read_addr_ptr(dev);
     plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", 500000);
 
 The dev_read\_...() interface is more convenient and works with both the
index 167b5a395f5876c850fd5a58756c634d41541ae8..6a4d861bf1e825b6a4363f8e4cb7afabb47e21b7 100644 (file)
@@ -912,7 +912,7 @@ int dwc_ahsata_probe(struct udevice *dev)
 #endif
        uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
                        ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
-       uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
+       uc_priv->mmio_base = dev_read_addr_ptr(dev);
 
        /* initialize adapter */
        ret = ahci_host_init(uc_priv);
index a1556fbf1740f165901f33396794d7d8ff7960e2..560f4c94f1ef89186cba3e093f540ccd36562d4e 100644 (file)
@@ -13,7 +13,7 @@ static void l2c310_of_parse_and_init(struct udevice *dev)
 {
        u32 tag[3] = { 0, 0, 0 };
        u32 saved_reg, prefetch;
-       struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
+       struct pl310_regs *regs = dev_read_addr_ptr(dev);
 
        /* Disable the L2 Cache */
        clrbits_le32(&regs->pl310_ctrl, L2X0_CTRL_EN);
index eda07d3f29e873ad036ccfc751051e75e6937aa3..fe3f9392b2ca30d72a0ede4c5974501cfff9654b 100644 (file)
@@ -119,7 +119,7 @@ static int v5l2_of_to_plat(struct udevice *dev)
        struct v5l2_plat *plat = dev_get_plat(dev);
        struct l2cache *regs;
 
-       regs = (struct l2cache *)(uintptr_t)dev_read_addr(dev);
+       regs = dev_read_addr_ptr(dev);
        plat->regs = regs;
 
        plat->iprefetch = -EINVAL;
index 1cbcc43489a1d04e581bb5e92b1dd298eb066e18..c97e44005ee1b6f61ef355da527dd38a5203d9f0 100644 (file)
@@ -232,7 +232,7 @@ static int mscc_sgpio_probe(struct udevice *dev)
        debug("probe: gpios = %d, bit-count = %d\n",
              uc_priv->gpio_count, priv->bitcount);
 
-       priv->regs = (u32 __iomem *)dev_read_addr(dev);
+       priv->regs = dev_read_addr_ptr(dev);
        uc_priv->bank_name = "sgpio";
 
        sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,
index 4291e496fa7fc3ddceee1f9c56cc114fc2000e5a..55105f2802c30f334fec9debcf0099d3e252b240 100644 (file)
@@ -339,8 +339,8 @@ static int gpio_tegra_bind(struct udevice *parent)
        if (len < 0)
                return len;
        bank_count = len / 3 / sizeof(u32);
-       ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
-       if ((ulong)ctlr == FDT_ADDR_T_NONE)
+       ctlr = dev_read_addr_ptr(parent);
+       if (!ctlr)
                return -EINVAL;
        }
 #endif
index 510838d2f5250bbf7a27d1917602501a7e806674..fa8d630b4658628691621a997e83e434af4addf8 100644 (file)
@@ -268,7 +268,7 @@ static int xilinx_gpio_of_to_plat(struct udevice *dev)
        struct xilinx_gpio_plat *plat = dev_get_plat(dev);
        int is_dual;
 
-       plat->regs = (struct gpio_regs *)dev_read_addr(dev);
+       plat->regs = dev_read_addr_ptr(dev);
 
        plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0);
        plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0);
index c1672ca18e1144051538fbdd19be995d3d07d4ef..1a8920720639d8fe31e20873dc110d16afdf7641 100644 (file)
@@ -479,9 +479,9 @@ static int cdns_i2c_of_to_plat(struct udevice *dev)
        struct clk clk;
        int ret;
 
-       i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
+       i2c_bus->regs = dev_read_addr_ptr(dev);
        if (!i2c_bus->regs)
-               return -ENOMEM;
+               return -EINVAL;
 
        if (pdata)
                i2c_bus->quirks = pdata->quirks;
index 2394e9d0fb4a74e648a1e6607b55855e248f072e..5864a1ad5bce0ee91948c4078e78e46a86ae8bc8 100644 (file)
@@ -364,8 +364,8 @@ static int tegra_i2c_probe(struct udevice *dev)
 
        i2c_bus->id = dev_seq(dev);
        i2c_bus->type = dev_get_driver_data(dev);
-       i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
-       if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
+       i2c_bus->regs = dev_read_addr_ptr(dev);
+       if (!i2c_bus->regs) {
                debug("%s: Cannot get regs address\n", __func__);
                return -EINVAL;
        }
index 42a61343645ab55b0160de8830efd814d53f17da..fd667aeafdaa084ebba42859f3b0a797311aad92 100644 (file)
@@ -584,7 +584,7 @@ static int am654_sdhci_of_to_plat(struct udevice *dev)
        int ret;
 
        host->name = dev->name;
-       host->ioaddr = (void *)dev_read_addr(dev);
+       host->ioaddr = dev_read_addr_ptr(dev);
        plat->non_removable = dev_read_bool(dev, "non-removable");
 
        if (plat->flags & DLL_PRESENT) {
index 05ca3612809b49355a6e2e19f5e6e9e9b19ee44b..3a3d23aec00a9e384db7a3ecc55666592adf54e8 100644 (file)
@@ -506,7 +506,7 @@ static int davinci_mmc_of_to_plat(struct udevice *dev)
        struct davinci_mmc_plat *plat = dev_get_plat(dev);
        struct mmc_config *cfg = &plat->cfg;
 
-       plat->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
+       plat->reg_base = dev_read_addr_ptr(dev);
        cfg->f_min = 200000;
        cfg->f_max = 25000000;
        cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
index 9f5da6d6339b34ae68cfb09bcf498d476d4608ac..a330bbf8cbe2df2da27f3131a893938f4bceaad2 100644 (file)
@@ -74,7 +74,7 @@ static int piton_mmc_ofdata_to_platdata(struct udevice *dev)
        struct mmc *mmc;
        struct blk_desc *bdesc;
 
-       priv->base_addr = (void *)dev_read_addr(dev);
+       priv->base_addr = dev_read_addr_ptr(dev);
        cfg = &plat->cfg;
        cfg->name = "PITON MMC";
        cfg->host_caps = MMC_MODE_8BIT;
index 760eca40590cd3e69c90ff7d601d6faf758481e7..f76fee3ea0f568082e5543eb07675464a45c23e0 100644 (file)
@@ -708,7 +708,7 @@ static int tegra_mmc_probe(struct udevice *dev)
 
        cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
-       priv->reg = (void *)dev_read_addr(dev);
+       priv->reg = dev_read_addr_ptr(dev);
 
        ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
        if (ret) {
index 9dc310663f296b1f6da612ada778d62f9fb71966..e44868aaec510c93d27dfb6a1e693e113e9d07ad 100644 (file)
@@ -1196,9 +1196,9 @@ static int arasan_sdhci_of_to_plat(struct udevice *dev)
        arasan_dt_parse_clk_phases(dev);
 #endif
 
-       priv->host->ioaddr = (void *)dev_read_addr(dev);
-       if (IS_ERR(priv->host->ioaddr))
-               return PTR_ERR(priv->host->ioaddr);
+       priv->host->ioaddr = dev_read_addr_ptr(dev);
+       if (!priv->host->ioaddr)
+               return -EINVAL;
 
        priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
        priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
index 99e2681c14b56c5dc5775a30caf196a5a3d19465..587941290dcc5a784b524fb6179b0751a2065703 100644 (file)
@@ -1233,7 +1233,7 @@ static int arasan_probe(struct udevice *dev)
        ofnode child;
        int err = -1;
 
-       info->reg = (struct nand_regs *)dev_read_addr(dev);
+       info->reg = dev_read_addr_ptr(dev);
        mtd = nand_to_mtd(nand_chip);
        nand_set_controller_data(nand_chip, &arasan->nand_ctrl);
 
index 8de35731a53f24c36335ade0252830604d361aca..b7be6602f7cc386570c52935b14bcfa69e430599 100644 (file)
@@ -1174,7 +1174,7 @@ static int fdt_decode_nand(struct udevice *dev, struct nand_drv *info)
 {
        int ecc_strength;
 
-       info->reg = (struct nand_ctlr *)dev_read_addr(dev);
+       info->reg = dev_read_addr_ptr(dev);
        info->dma_glb = dev_read_addr_index_ptr(dev, 1);
        info->dma_nand = dev_read_addr_index_ptr(dev, 2);
        info->config.enabled = dev_read_enabled(dev);
index e54df4615e9ed1dfb85cfa745bd1e967b5c6bf6c..6abdc24bd30c097c9588ef3300812164b699d9e0 100644 (file)
@@ -538,7 +538,7 @@ static int mxic_nfc_probe(struct udevice *dev)
        ofnode child;
        int err;
 
-       nfc->regs = (void *)dev_read_addr(dev);
+       nfc->regs = dev_read_addr_ptr(dev);
 
        nfc->send_clk = devm_clk_get(dev, "send");
        if (IS_ERR(nfc->send_clk))
index d2801d48a3bf5d782e2a4bbad3bc9c51ea654c8e..139d978a49b32dd022d23aeccba039da1b66447e 100644 (file)
@@ -906,7 +906,7 @@ static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
 {
        int err;
 
-       config->reg = (struct nand_ctlr *)dev_read_addr(dev);
+       config->reg = dev_read_addr_ptr(dev);
        config->enabled = dev_read_enabled(dev);
        config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
        err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,
index 14cb2ba704360dec15d5a1b9fa0a593dd4a3a993..9e3ee7412d006dd0c202f7f651114aa5e8c59d07 100644 (file)
@@ -1085,7 +1085,7 @@ static int zynq_nand_probe(struct udevice *dev)
        int ondie_ecc_enabled = 0;
        int is_16bit_bw;
 
-       smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev);
+       smc->reg = dev_read_addr_ptr(dev);
        of_nand = dev_read_subnode(dev, "nand-controller@0,0");
        if (!ofnode_valid(of_nand)) {
                of_nand = dev_read_subnode(dev, "flash@e1000000");
index 6fb8a985d03732b7fea1de638458f7f1c291e02f..c0ebcdb1f68a66ed0b4ee8931860e32da0f221a5 100644 (file)
@@ -208,7 +208,7 @@ static int mvmdio_probe(struct udevice *dev)
 {
        struct mvmdio_priv *priv = dev_get_priv(dev);
 
-       priv->mdio_base = (void *)dev_read_addr(dev);
+       priv->mdio_base = dev_read_addr_ptr(dev);
        priv->type = (enum mvmdio_bus_type)dev_get_driver_data(dev);
 
        return 0;
index 038b810460cc069b3aecd9ef8b93707554376dc7..a0bcc8d3e55bfcf360a822f52c5bd67961f22da6 100644 (file)
@@ -97,7 +97,7 @@ static int qe_uec_mdio_probe(struct udevice *dev)
        u32 num = 0;
        int ret = -ENODEV;
 
-       priv->base = (struct ucc_mii_mng *)dev_read_addr(dev);
+       priv->base = dev_read_addr_ptr(dev);
        base = (fdt_size_t)priv->base;
 
        /*
index b0fc9caabbec70fd0232a31ce714124ef23f6a09..af0e55cd2f2cd99e654d1484a66fdb761f3128d9 100644 (file)
@@ -983,8 +983,8 @@ static int pcie_advk_of_to_plat(struct udevice *dev)
        struct pcie_advk *pcie = dev_get_priv(dev);
 
        /* Get the register base address */
-       pcie->base = (void *)dev_read_addr(dev);
-       if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
+       pcie->base = dev_read_addr_ptr(dev);
+       if (!pcie->base)
                return -EINVAL;
 
        return 0;
index e5a3d2d92ea12918e47714bbcdbb30a4d4bde5f3..609d9d4ec93d3f550d219acf16295e29e17cda9e 100644 (file)
@@ -149,9 +149,9 @@ static int sun50i_usb3_phy_probe(struct udevice *dev)
                return ret;
        }
 
-       priv->regs = (void __iomem *)dev_read_addr(dev);
-       if (IS_ERR(priv->regs))
-               return PTR_ERR(priv->regs);
+       priv->regs = dev_read_addr_ptr(dev);
+       if (!priv->regs)
+               return -EINVAL;
 
        return 0;
 }
index 14c3d8394df9c1bfa79b9d2bc2f133ec8763d7b1..05a9a2cf1d7cee3e9dbe1bfd984771525c50c1b5 100644 (file)
@@ -184,8 +184,8 @@ static int hsphy_probe(struct udevice *dev)
        struct hsphy_priv *priv = dev_get_priv(dev);
        int ret;
 
-       priv->base = (void *)dev_read_addr(dev);
-       if ((ulong)priv->base == FDT_ADDR_T_NONE)
+       priv->base = dev_read_addr_ptr(dev);
+       if (!priv->base)
                return -EINVAL;
 
        ret = reset_get_by_name(dev, "phy", &priv->phy_rst);
index 4e816879c6a1e72faf706f1779599432047a7151..1b03a3c43dc8d78cf10fedf32103cc9aa2b9c9ef 100644 (file)
@@ -115,8 +115,8 @@ static int ssphy_probe(struct udevice *dev)
        struct ssphy_priv *priv = dev_get_priv(dev);
        int ret;
 
-       priv->base = (void *)dev_read_addr(dev);
-       if ((ulong)priv->base == FDT_ADDR_T_NONE)
+       priv->base = dev_read_addr_ptr(dev);
+       if (!priv->base)
                return -EINVAL;
 
        ret = ssphy_clk_init(dev, priv);
index 5ae41fbeeec54f79363e20afdf397a6024357eae..66c75f98e6d148d5810ad963b0b182701204ec18 100644 (file)
@@ -93,8 +93,8 @@ static int rockchip_p3phy_probe(struct udevice *dev)
        struct udevice *syscon;
        int ret;
 
-       priv->mmio = (void __iomem *)dev_read_addr(dev);
-       if ((fdt_addr_t)priv->mmio == FDT_ADDR_T_NONE)
+       priv->mmio = dev_read_addr_ptr(dev);
+       if (!priv->mmio)
                return -EINVAL;
 
        ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
index ca63b856e13bee30491f17a9cfe7877d9b19f3b4..47c69dd6c4537fbed4c411b60d257ee386d35baf 100644 (file)
@@ -674,9 +674,9 @@ static int rockchip_tcphy_probe(struct udevice *dev)
        unsigned int reg;
        int index, ret;
 
-       priv->reg_base = (void __iomem *)dev_read_addr(dev);
-       if (IS_ERR(priv->reg_base))
-               return PTR_ERR(priv->reg_base);
+       priv->reg_base = dev_read_addr_ptr(dev);
+       if (!priv->reg_base)
+               return -EINVAL;
 
        ret = dev_read_u32_index(dev, "reg", 1, &reg);
        if (ret) {
index 95fc26458b89d4f6e5619465de1bd2699aa5fa16..87034706060c306704a17d7c9f7b543f7237776c 100644 (file)
@@ -59,7 +59,7 @@ static int tegra_pwm_of_to_plat(struct udevice *dev)
 {
        struct tegra_pwm_priv *priv = dev_get_priv(dev);
 
-       priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
+       priv->regs = dev_read_addr_ptr(dev);
 
        return 0;
 }
index 9bb9b7d3b8dd3323182982d2fdcdca919d24e5e6..1847d1f6ecd23416aec899a9aa1a0605d101137c 100644 (file)
@@ -259,9 +259,9 @@ static int zynq_serial_of_to_plat(struct udevice *dev)
 {
        struct zynq_uart_plat *plat = dev_get_plat(dev);
 
-       plat->regs = (struct uart_zynq *)dev_read_addr(dev);
-       if (IS_ERR(plat->regs))
-               return PTR_ERR(plat->regs);
+       plat->regs = dev_read_addr_ptr(dev);
+       if (!plat->regs)
+               return -EINVAL;
 
        return 0;
 }
index 78892173dc1f40b90cb18cddc7d0674aec493528..7d15390c56b327227ccc3d91bab27a98c0578961 100644 (file)
@@ -56,7 +56,7 @@ static int mpc8xxx_spi_of_to_plat(struct udevice *dev)
        struct clk clk;
        int ret;
 
-       priv->spi = (spi8xxx_t *)dev_read_addr(dev);
+       priv->spi = dev_read_addr_ptr(dev);
 
        ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
                                        ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
index 2a01ea061fbb0e92b48915bde6b7f2e5c07cebdc..95bea0da1b357477fc7aff22562ba8332237d41b 100644 (file)
@@ -217,7 +217,7 @@ static int mscc_bb_spi_probe(struct udevice *bus)
 
        debug("%s: loaded, priv %p\n", __func__, priv);
 
-       priv->regs = (void __iomem *)dev_read_addr(bus);
+       priv->regs = dev_read_addr_ptr(bus);
 
        priv->deactivate_delay_us =
                dev_read_u32_default(bus, "spi-deactivate-delay", 0);
index 861423bef3fa2c6f2b5ec86b30c6bb5e1404544f..7dd1fe75e041c24f883fcfa4d8060725fb427689 100644 (file)
@@ -334,7 +334,7 @@ static int sh_qspi_of_to_plat(struct udevice *dev)
 {
        struct sh_qspi_slave *plat = dev_get_plat(dev);
 
-       plat->regs = (struct sh_qspi_regs *)dev_read_addr(dev);
+       plat->regs = dev_read_addr_ptr(dev);
 
        return 0;
 }
index 6aae9f7955617b7784a81672d8b078ce855cd459..f663b9dcbb161c44e97660d4eb87f211755efa7a 100644 (file)
@@ -508,7 +508,7 @@ static int mxic_spi_probe(struct udevice *bus)
 {
        struct mxic_spi_priv *priv = dev_get_priv(bus);
 
-       priv->regs = (void *)dev_read_addr(bus);
+       priv->regs = dev_read_addr_ptr(bus);
 
        priv->send_clk = devm_clk_get(bus, "send_clk");
        if (IS_ERR(priv->send_clk))
index 9e6255a172a4d4c2b37a8f14356e1b3065b3c685..33575fe75754006c08fb8f208c39685caa6611e9 100644 (file)
@@ -114,7 +114,7 @@ static int xilinx_spi_probe(struct udevice *bus)
        struct xilinx_spi_priv *priv = dev_get_priv(bus);
        struct xilinx_spi_regs *regs;
 
-       regs = priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
+       regs = priv->regs = dev_read_addr_ptr(bus);
        priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
 
        writel(SPISSR_RESET_VALUE, &regs->srr);
index 13e730b88355497eb9853141d4f5459e8ed1d908..8dd29edd3de8d503ce41cc28545a057d0a53e886 100644 (file)
@@ -1880,7 +1880,7 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
 
        hba->dev = ufs_dev;
        hba->ops = hba_ops;
-       hba->mmio_base = (void *)dev_read_addr(ufs_dev);
+       hba->mmio_base = dev_read_addr_ptr(ufs_dev);
 
        /* Set descriptor lengths to specification defaults */
        ufshcd_def_desc_sizes(hba);
index 76562bd749f7ebcf882a2de85a8ec800eeb66aab..2cf16256703d0dd0e149c9be38325a84432c5e55 100644 (file)
@@ -723,7 +723,7 @@ static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
 {
        const char *phy, *mode;
 
-       config->reg = (struct usb_ctlr *)dev_read_addr(dev);
+       config->reg = dev_read_addr_ptr(dev);
        debug("reg=%p\n", config->reg);
        mode = dev_read_string(dev, "dr_mode");
        if (mode) {
index a4606923ffc1f1d9f220f4f0732d6fa6b39fa257..92e388ac1e42b9ed7dda962caf4553a6e2ee3a5a 100644 (file)
@@ -800,8 +800,8 @@ static int dw_mipi_dsi_init(struct udevice *dev,
        dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
        device->host = &dsi->dsi_host;
 
-       dsi->base = (void *)dev_read_addr(device->dev);
-       if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) {
+       dsi->base = dev_read_addr_ptr(device->dev);
+       if (!dsi->base) {
                dev_err(device->dev, "dsi dt register address error\n");
                return -EINVAL;
        }
index e21ac7e30364a6c4e2c58168f1cb55fc658bc124..dab9902fda73ce51b8ff446e6a65e82672b10fd5 100644 (file)
@@ -447,7 +447,7 @@ int rk_vop_probe(struct udevice *dev)
        efi_add_memory_map(plat->base, plat->size, EFI_RESERVED_MEMORY_TYPE);
 #endif
 
-       priv->regs = (struct rk3288_vop *)dev_read_addr(dev);
+       priv->regs = dev_read_addr_ptr(dev);
 
        /*
         * Try all the ports until we find one that works. In practice this
index e6347bb8da6a85f93d3517274aeb6a0855135b3e..a7420fb2ee7ff69822f7ca0b10392aa04e218fa3 100644 (file)
@@ -427,8 +427,8 @@ static int stm32_dsi_probe(struct udevice *dev)
 
        device->dev = dev;
 
-       priv->base = (void *)dev_read_addr(dev);
-       if ((fdt_addr_t)priv->base == FDT_ADDR_T_NONE) {
+       priv->base = dev_read_addr_ptr(dev);
+       if (!priv->base) {
                dev_err(dev, "dsi dt register address error\n");
                return -EINVAL;
        }
index 58b6434a485a7f85139bf4cd68bb05de2e6cf4f6..f48badc517a8296e377e344048395eb2c1ac6c46 100644 (file)
@@ -507,8 +507,8 @@ static int stm32_ltdc_probe(struct udevice *dev)
        ulong rate;
        int ret;
 
-       priv->regs = (void *)dev_read_addr(dev);
-       if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
+       priv->regs = dev_read_addr_ptr(dev);
+       if (!priv->regs) {
                dev_err(dev, "ltdc dt register address error\n");
                return -EINVAL;
        }
index 78ab3f99c4de87085a48e632ba44e89b679f8d1a..9261cc9384a2b628ae19dc5fafdeee2ba001cda1 100644 (file)
@@ -361,7 +361,7 @@ static int display_init(struct udevice *dev, void *lcdbase,
                return ret;
        }
 
-       dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
+       dc_ctlr = dev_read_addr_ptr(dev);
        if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
                debug("%s: Failed to decode display timing\n", __func__);
                return -EINVAL;
index ef1a2e6dc0fc179b88d8c2f90868ad500e58db46..f291db3dc7664896560978c24df73db31b8f209a 100644 (file)
@@ -765,7 +765,7 @@ int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev,
 
        /* Use the first display controller */
        debug("%s\n", __func__);
-       disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);
+       disp_ctrl = dev_read_addr_ptr(dc_dev);
 
        tegra_dc_sor_enable_dc(disp_ctrl);
        tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
@@ -978,7 +978,7 @@ int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev)
 
        debug("%s\n", __func__);
        /* Use the first display controller */
-       disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);
+       disp_ctrl = dev_read_addr_ptr(dev);
 
        /* Sleep mode */
        tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
@@ -1047,7 +1047,7 @@ static int tegra_sor_of_to_plat(struct udevice *dev)
        struct tegra_dc_sor_data *priv = dev_get_priv(dev);
        int ret;
 
-       priv->base = (void *)dev_read_addr(dev);
+       priv->base = dev_read_addr_ptr(dev);
 
        priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
        if (IS_ERR(priv->pmc_base))
index 88043fc18c50948a98e2aeb4b5c1a9abe6d4f5d3..2734754ecde7574b6f247c64aa88c3a84144321f 100644 (file)
@@ -387,8 +387,8 @@ static int tilcdc_of_to_plat(struct udevice *dev)
 {
        struct tilcdc_priv *priv = dev_get_priv(dev);
 
-       priv->regs = (struct tilcdc_regs *)dev_read_addr(dev);
-       if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
+       priv->regs = dev_read_addr_ptr(dev);
+       if (!priv->regs) {
                dev_err(dev, "failed to get base address\n");
                return -EINVAL;
        }
index 6dfdd31c8b8f9fa893127deb12d3f7e7daf18f41..743ab6487bcd115754a6bae9ca508ef43eaabab6 100644 (file)
@@ -271,9 +271,9 @@ static int cdns_wdt_of_to_plat(struct udevice *dev)
 {
        struct cdns_wdt_priv *priv = dev_get_priv(dev);
 
-       priv->regs = (struct cdns_regs *)dev_read_addr(dev);
-       if (IS_ERR(priv->regs))
-               return PTR_ERR(priv->regs);
+       priv->regs = dev_read_addr_ptr(dev);
+       if (!priv->regs)
+               return -EINVAL;
 
        priv->rst = dev_read_bool(dev, "reset-on-timeout");
 
index 0d6fb1206546592e83d104d0763f23dc9738e151..6d58fd3cfdab8a3e215d6c60967836da590029e1 100644 (file)
@@ -116,9 +116,9 @@ static int sp805_wdt_of_to_plat(struct udevice *dev)
        struct sp805_wdt_priv *priv = dev_get_priv(dev);
        struct clk clk;
 
-       priv->reg = (void __iomem *)dev_read_addr(dev);
-       if (IS_ERR(priv->reg))
-               return PTR_ERR(priv->reg);
+       priv->reg = dev_read_addr_ptr(dev);
+       if (!priv->reg)
+               return -EINVAL;
 
        if (!clk_get_by_index(dev, 0, &clk))
                priv->clk_rate = clk_get_rate(&clk);
index 1687a4599fce6d93c396afc314e2dadc97882938..0f9fb02002897c4543b88e93a85011041b7a03e5 100644 (file)
@@ -94,9 +94,9 @@ static int xlnx_wdt_of_to_plat(struct udevice *dev)
 {
        struct xlnx_wdt_plat *plat = dev_get_plat(dev);
 
-       plat->regs = (struct watchdog_regs *)dev_read_addr(dev);
-       if (IS_ERR(plat->regs))
-               return PTR_ERR(plat->regs);
+       plat->regs = dev_read_addr_ptr(dev);
+       if (!plat->regs)
+               return -EINVAL;
 
        plat->enable_once = dev_read_u32_default(dev, "xlnx,wdt-enable-once",
                                                 0);