mx31: Fix PDR0_CSI_PODF

The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0
register is actually composed of two bit-fields: one pre-divider and one
post-divider. This patch fixes the CCM access macros and the code using them
accordingly.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index c3919be7f4244966c5e8cd077467fb9fce6d1ed5..8fd3d08069be2ce96bf708c3e14a05ab75185738 100644 (file)
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -569,7 +569,8 @@ struct esdc_regs {
 
 #define MX31_IIM_BASE_ADDR     0x5001C000
 
-#define PDR0_CSI_PODF(x)       (((x) & 0x1ff) << 23)
+#define PDR0_CSI_PODF(x)       (((x) & 0x3f) << 26)
+#define PDR0_CSI_PRDF(x)       (((x) & 0x7) << 23)
 #define PDR0_PER_PODF(x)       (((x) & 0x1f) << 16)
 #define PDR0_HSP_PODF(x)       (((x) & 0x7) << 11)
 #define PDR0_NFC_PODF(x)       (((x) & 0x7) << 8)
@@ -592,7 +593,8 @@ struct esdc_regs {
 #define PLL_MFI(x)             (((x) & 0xf) << 10)
 #define PLL_MFN(x)             (((x) & 0x3ff) << 0)
 
-#define GET_PDR0_CSI_PODF(x)   (((x) >> 23) & 0x1ff)
+#define GET_PDR0_CSI_PODF(x)   (((x) >> 26) & 0x3f)
+#define GET_PDR0_CSI_PRDF(x)   (((x) >> 23) & 0x7)
 #define GET_PDR0_PER_PODF(x)   (((x) >> 16) & 0x1f)
 #define GET_PDR0_HSP_PODF(x)   (((x) >> 11) & 0x7)
 #define GET_PDR0_NFC_PODF(x)   (((x) >> 8) & 0x7)

diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S
index 5c18bc19648a9bb038415bf2b78e6ecb95894eb7..29720658225594c3a422c2470e59c433716b939d 100644 (file)
--- a/board/freescale/mx31ads/lowlevel_init.S
+++ b/board/freescale/mx31ads/lowlevel_init.S
@@ -246,8 +246,8 @@ lowlevel_init:
        /* COSR */
        str     r1, [r0, #0x1c]
 
-       /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
-/*     REG     CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
+       /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
+/*     REG     CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
 
        /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
 /*     REG     CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/

diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c
index 02e75edb4028eea1f52c895ba54a70107214c3b6..143fcefedf55e710c055d92d859eebc2ec225724 100644 (file)
--- a/board/hale/tt01/tt01.c
+++ b/board/hale/tt01/tt01.c
@@ -52,7 +52,7 @@ static void board_setup_clocks(void)
        writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
 
        /* Set up clock to 532MHz */
-       writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
+       writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
                        PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
                        PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
                        PDR0_MCU_PODF(0), &ccm->pdr0);

diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S
index c47137d097a3ac632b94fdfb87dafe364dea1457..4dd78b660a420bcd7785023c203ba0b85e72ff75 100644 (file)
--- a/board/imx31_phycore/lowlevel_init.S
+++ b/board/imx31_phycore/lowlevel_init.S
@@ -54,7 +54,7 @@ lowlevel_init:
        REG     CCM_CCMR, 0x074B0BF5 | CCMR_MPE
        REG     CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
 
-       REG     CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
+       REG     CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
 
        REG     CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
 

diff --git a/board/logicpd/imx31_litekit/lowlevel_init.S b/board/logicpd/imx31_litekit/lowlevel_init.S
index 95b0c080c5d1cd4f45643dd64b01bcbd9d41db86..0ce890549eaac8368a18a03a8c72d6e947ec5f99 100644 (file)
--- a/board/logicpd/imx31_litekit/lowlevel_init.S
+++ b/board/logicpd/imx31_litekit/lowlevel_init.S
@@ -54,7 +54,7 @@ lowlevel_init:
        REG     CCM_CCMR, 0x074B0BF5 | CCMR_MPE
        REG     CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
 
-       REG     CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
+       REG     CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
 
        REG     CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
        REG     CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)

diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index b272674f820e8a193603dc39aff5418aee84c7d3..223b5b0bb9291b8911f0d2437004c1fd7334b873 100644 (file)
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -203,11 +203,11 @@
 
 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
 #define CCM_CCMR_SETUP         0x074B0BF5
-#define CCM_PDR0_SETUP_532MHZ  (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
-                                PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |     \
-                                PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |     \
-                                PDR0_MCU_PODF(0))
-#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |   \
+#define CCM_PDR0_SETUP_532MHZ  (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
+                                PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
+                                PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
+                                PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
+#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
                                 PLL_MFN(12))
 
 #define ESDMISC_MDDR_SETUP     0x00000004