global: Migrate CONFIG_SAR_REG to CFG

Perform a simple rename of CONFIG_SAR_REG to CFG_SAR_REG

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
index 7f8e156a6bdcd49935a4fe2c12364ad82492996f..67f0b3ec67727866872b8bff5cd160600973084a 100644 (file)
--- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
+++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
@@ -15,7 +15,7 @@
 #define KW_REGS_PHY_BASE               KW88F6281_REGS_PHYS_BASE
 
 /* TCLK Core Clock definition */
-#define CFG_SYS_TCLK                   ((readl(CONFIG_SAR_REG) & BIT(21)) ? \
+#define CFG_SYS_TCLK                   ((readl(CFG_SAR_REG) & BIT(21)) ? \
                                        166666667 : 200000000)
 
 #endif /* _ASM_ARCH_KW88F6281_H */

diff --git a/arch/arm/mach-kirkwood/include/mach/soc.h b/arch/arm/mach-kirkwood/include/mach/soc.h
index 5f545c6f4349be820545ebd99c9f71004fc07d7c..4a7efc50f67a6554100b29f18c8bfd78d256240b 100644 (file)
--- a/arch/arm/mach-kirkwood/include/mach/soc.h
+++ b/arch/arm/mach-kirkwood/include/mach/soc.h
@@ -62,7 +62,7 @@
 #define MVCPU_WIN_ENABLE       KWCPU_WIN_ENABLE
 #define MVCPU_WIN_DISABLE      KWCPU_WIN_DISABLE
 
-#define CONFIG_SAR_REG         (KW_MPP_BASE + 0x0030)
+#define CFG_SAR_REG            (KW_MPP_BASE + 0x0030)
 
 #if defined (CONFIG_KW88F6281)
 #include <asm/arch/kw88f6281.h>

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 9139df1ae2480057a9f646c8a3d955fb41e243ec..329d13691f0ecfa472d5b1b288ce9ddce1bd4be0 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -83,7 +83,7 @@ u32 get_boot_device(void)
        /*
         * Now check the SAR register for the strapped boot-device
         */
-       val = readl(CONFIG_SAR_REG);    /* SAR - Sample At Reset */
+       val = readl(CFG_SAR_REG);       /* SAR - Sample At Reset */
        boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
        debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
        switch (boot_device) {
@@ -197,7 +197,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
        val = readl(CFG_SAR2_REG);      /* SAR - Sample At Reset */
 #else
-       val = readl(CONFIG_SAR_REG);    /* SAR - Sample At Reset */
+       val = readl(CFG_SAR_REG);       /* SAR - Sample At Reset */
 #endif
        freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
 #if defined(SAR2_CPU_FREQ_MASK)

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 1210d26c74617c635f9e035658cf328949d8ca36..6edd2e2d79c7b579201fe21891c3c8ca7d77d4e1 100644 (file)
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -134,7 +134,7 @@
 
 #if defined(CONFIG_ARMADA_375)
 /* SAR values for Armada 375 */
-#define CONFIG_SAR_REG         (MVEBU_REGISTER(0xe8200))
+#define CFG_SAR_REG            (MVEBU_REGISTER(0xe8200))
 #define CFG_SAR2_REG           (MVEBU_REGISTER(0xe8204))
 
 #define SAR_CPU_FREQ_OFFS      17
@@ -146,11 +146,11 @@
 #define BOOT_FROM_UART         0x30
 #define BOOT_FROM_SPI          0x38
 
-#define CFG_SYS_TCLK           ((readl(CONFIG_SAR_REG) & BIT(20)) ? \
+#define CFG_SYS_TCLK           ((readl(CFG_SAR_REG) & BIT(20)) ? \
                                 200000000 : 166000000)
 #elif defined(CONFIG_ARMADA_38X)
 /* SAR values for Armada 38x */
-#define CONFIG_SAR_REG         (MVEBU_REGISTER(0x18600))
+#define CFG_SAR_REG            (MVEBU_REGISTER(0x18600))
 
 #define SAR_CPU_FREQ_OFFS      10
 #define SAR_CPU_FREQ_MASK      (0x1f << SAR_CPU_FREQ_OFFS)
@@ -169,11 +169,11 @@
 #define BOOT_FROM_MMC          0x30
 #define BOOT_FROM_MMC_ALT      0x31
 
-#define CFG_SYS_TCLK           ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
+#define CFG_SYS_TCLK           ((readl(CFG_SAR_REG) & BIT(15)) ? \
                                 200000000 : 250000000)
 #elif defined(CONFIG_ARMADA_MSYS)
 /* SAR values for MSYS */
-#define CONFIG_SAR_REG         (MBUS_DFX_BASE  + 0xf8200)
+#define CFG_SAR_REG            (MBUS_DFX_BASE  + 0xf8200)
 #define CFG_SAR2_REG           (MBUS_DFX_BASE  + 0xf8204)
 
 #define SAR_CPU_FREQ_OFFS      18
@@ -191,7 +191,7 @@
 #define CFG_SYS_TCLK           200000000       /* 200MHz */
 #elif defined(CONFIG_ARMADA_XP)
 /* SAR values for Armada XP */
-#define CONFIG_SAR_REG         (MVEBU_REGISTER(0x18230))
+#define CFG_SAR_REG            (MVEBU_REGISTER(0x18230))
 #define CFG_SAR2_REG           (MVEBU_REGISTER(0x18234))
 
 #define SAR_CPU_FREQ_OFFS      21