]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
pxa: add support for D- and I- caches
authorVasily Khoruzhick <anarsoul@gmail.com>
Mon, 21 Mar 2016 01:37:07 +0000 (18:37 -0700)
committerTom Rini <trini@konsulko.com>
Sun, 27 Mar 2016 13:13:00 +0000 (09:13 -0400)
Tested with OHCI and pxafb drivers - no issues found

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
arch/arm/cpu/pxa/Makefile
arch/arm/cpu/pxa/cache.c [new file with mode: 0644]
arch/arm/cpu/pxa/pxa2xx.c
include/configs/pxa-common.h

index 3ee08cd188756807947910f12928366b77c7cab0..79fcb7398b3f58edb4367b8d82310287e8bada42 100644 (file)
@@ -14,3 +14,4 @@ obj-y += cpuinfo.o
 obj-y  += timer.o
 obj-y  += usb.o
 obj-y  += relocate.o
+obj-y  += cache.o
diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c
new file mode 100644 (file)
index 0000000..7aba112
--- /dev/null
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2016 Vasily Khoruzhick <anarsoul@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <common.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE      32
+#endif
+
+void invalidate_dcache_all(void)
+{
+       /* Flush/Invalidate I cache */
+       asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0));
+       /* Flush/Invalidate D cache */
+       asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
+}
+
+void flush_dcache_all(void)
+{
+       return invalidate_dcache_all();
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+       start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+       stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+
+       while (start <= stop) {
+               asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
+               start += CONFIG_SYS_CACHELINE_SIZE;
+       }
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+       return invalidate_dcache_range(start, stop);
+}
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+/*
+ * Stub implementations for l2 cache operations
+ */
+
+__weak void l2_cache_disable(void) {}
+
+#if defined CONFIG_SYS_THUMB_BUILD
+__weak void invalidate_l2_cache(void) {}
+#endif
index 2f12fb9c82553c74263e0b41e6116540cd5a3bfe..77f0ef2de4ae8e9297ae8d77a2d31eb4cf9a5798 100644 (file)
@@ -284,3 +284,13 @@ void reset_cpu(ulong ignored)
        for (;;)
                ;
 }
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+       icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+       dcache_enable();
+#endif
+}
index 4c1c2c7e8d3ba59e1f8d859724d39c2b9f8a2953..729568755bced03dae42e8f84dcd66200bc5bb0d 100644 (file)
@@ -10,6 +10,7 @@
 #define        __CONFIG_PXA_COMMON_H__
 
 #define        CONFIG_DISPLAY_CPUINFO
+#define        CONFIG_SYS_ARM_CACHE_WRITETHROUGH
 
 /*
  * KGDB