fsl_esdhc: Fix DMA transfer completion waiting loop

Rework the waiting for transfer completion loop condition
to continue waiting until both Transfer Complete and DMA End
interrupts occur. Checking of DLA bit in Present State register
looks not needed in addition to interrupts status checking,
so it can be removed from the condition. Also, DMA Error
condition is added to the list of data errors, checked in the loop.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 737b812b54085421ec0347110dcce32aa3b1dd6f..e945c0a470ca85667026a422933e7669effcb6a2 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -397,8 +397,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
                        if (irqstat & DATA_ERR)
                                return COMM_ERR;
-               } while (!(irqstat & IRQSTAT_TC) &&
-                               (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
+               } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 #endif
                if (data->flags & MMC_DATA_READ)
                        check_and_invalidate_dcache_range(cmd, data);

diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 0a1a0715e957d0d35286f9843dfcbfe957f6531f..67d6057b5ff4637a0c6fdcd372cfc6c09c98a71a 100644 (file)
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -63,7 +63,9 @@
 #define IRQSTAT_CC             (0x00000001)
 
 #define CMD_ERR                (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
-#define DATA_ERR       (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE)
+#define DATA_ERR       (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
+                               IRQSTAT_DMAE)
+#define DATA_COMPLETE  (IRQSTAT_TC | IRQSTAT_DINT)
 
 #define IRQSTATEN              0x0002e034
 #define IRQSTATEN_DMAE         (0x10000000)