ARM: dts: rmobile: Import R8A7794 DTS from Linux 4.15-rc8

Import the Renesas R8A7794 DTS and headers from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/arch/arm/dts/r8a7794-alt.dts b/arch/arm/dts/r8a7794-alt.dts
new file mode 100644 (file)
index 0000000..0e975d0
--- /dev/null
+++ b/arch/arm/dts/r8a7794-alt.dts
@@ -0,0 +1,414 @@
+/*
+ * Device Tree Source for the Alt board
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+/dts-v1/;
+#include "r8a7794.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       model = "Alt";
+       compatible = "renesas,alt", "renesas,r8a7794";
+
+       aliases {
+               serial0 = &scif2;
+               i2c10 = &gpioi2c4;
+               i2c12 = &i2cexio4;
+       };
+
+       chosen {
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0 0x40000000 0 0x40000000>;
+       };
+
+       d3_3v: regulator-d3-3v {
+               compatible = "regulator-fixed";
+               regulator-name = "D3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       vcc_sdhi0: regulator-vcc-sdhi0 {
+               compatible = "regulator-fixed";
+
+               regulator-name = "SDHI0 Vcc";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       vccq_sdhi0: regulator-vccq-sdhi0 {
+               compatible = "regulator-gpio";
+
+               regulator-name = "SDHI0 VccQ";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
+               gpios-states = <1>;
+               states = <3300000 1
+                         1800000 0>;
+       };
+
+       vcc_sdhi1: regulator-vcc-sdhi1 {
+               compatible = "regulator-fixed";
+
+               regulator-name = "SDHI1 Vcc";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       vccq_sdhi1: regulator-vccq-sdhi1 {
+               compatible = "regulator-gpio";
+
+               regulator-name = "SDHI1 VccQ";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+               gpios-states = <1>;
+               states = <3300000 1
+                         1800000 0>;
+       };
+
+       lbsc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+       };
+
+       vga-encoder {
+               compatible = "adi,adv7123";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               adv7123_in: endpoint {
+                                       remote-endpoint = <&du_out_rgb1>;
+                               };
+                       };
+                       port@1 {
+                               reg = <1>;
+                               adv7123_out: endpoint {
+                                       remote-endpoint = <&vga_in>;
+                               };
+                       };
+               };
+       };
+
+       vga {
+               compatible = "vga-connector";
+
+               port {
+                       vga_in: endpoint {
+                               remote-endpoint = <&adv7123_out>;
+                       };
+               };
+       };
+
+       x2_clk: x2-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <74250000>;
+       };
+
+       x13_clk: x13-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <148500000>;
+       };
+
+       gpioi2c4: i2c-10 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "i2c-gpio";
+               status = "disabled";
+               gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
+                        &gpio4 8 GPIO_ACTIVE_HIGH /* scl */
+                       >;
+               i2c-gpio,delay-us = <5>;
+       };
+
+       /*
+        * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
+        * A fallback to GPIO is provided.
+        */
+       i2cexio4: i2c-14 {
+               compatible = "i2c-demux-pinctrl";
+               i2c-parent = <&i2c4>, <&gpioi2c4>;
+               i2c-bus-name = "i2c-exio4";
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+};
+
+&du {
+       pinctrl-0 = <&du_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+                <&x13_clk>, <&x2_clk>;
+       clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+
+       ports {
+               port@1 {
+                       endpoint {
+                               remote-endpoint = <&adv7123_in>;
+                       };
+               };
+       };
+};
+
+&extal_clk {
+       clock-frequency = <20000000>;
+};
+
+&pfc {
+       pinctrl-0 = <&scif_clk_pins>;
+       pinctrl-names = "default";
+
+       du_pins: du {
+               groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
+               function = "du1";
+       };
+
+       scif2_pins: scif2 {
+               groups = "scif2_data";
+               function = "scif2";
+       };
+
+       scif_clk_pins: scif_clk {
+               groups = "scif_clk";
+               function = "scif_clk";
+       };
+
+       ether_pins: ether {
+               groups = "eth_link", "eth_mdio", "eth_rmii";
+               function = "eth";
+       };
+
+       phy1_pins: phy1 {
+               groups = "intc_irq8";
+               function = "intc";
+       };
+
+       i2c1_pins: i2c1 {
+               groups = "i2c1";
+               function = "i2c1";
+       };
+
+       i2c4_pins: i2c4 {
+               groups = "i2c4";
+               function = "i2c4";
+       };
+
+       vin0_pins: vin0 {
+               groups = "vin0_data8", "vin0_clk";
+               function = "vin0";
+       };
+
+       mmcif0_pins: mmcif0 {
+               groups = "mmc_data8", "mmc_ctrl";
+               function = "mmc";
+       };
+
+       sdhi0_pins: sd0 {
+               groups = "sdhi0_data4", "sdhi0_ctrl";
+               function = "sdhi0";
+               power-source = <3300>;
+       };
+
+       sdhi0_pins_uhs: sd0_uhs {
+               groups = "sdhi0_data4", "sdhi0_ctrl";
+               function = "sdhi0";
+               power-source = <1800>;
+       };
+
+       sdhi1_pins: sd1 {
+               groups = "sdhi1_data4", "sdhi1_ctrl";
+               function = "sdhi1";
+               power-source = <3300>;
+       };
+
+       sdhi1_pins_uhs: sd1_uhs {
+               groups = "sdhi1_data4", "sdhi1_ctrl";
+               function = "sdhi1";
+               power-source = <1800>;
+       };
+};
+
+&cmt0 {
+       status = "okay";
+};
+
+&pfc {
+       qspi_pins: qspi {
+               groups = "qspi_ctrl", "qspi_data4";
+               function = "qspi";
+       };
+};
+
+&ether {
+       pinctrl-0 = <&ether_pins &phy1_pins>;
+       pinctrl-names = "default";
+
+       phy-handle = <&phy1>;
+       renesas,ether-link-active-low;
+       status = "okay";
+
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+               interrupt-parent = <&irqc0>;
+               interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+               micrel,led-mode = <1>;
+       };
+};
+
+&mmcif0 {
+       pinctrl-0 = <&mmcif0_pins>;
+       pinctrl-names = "default";
+
+       vmmc-supply = <&d3_3v>;
+       vqmmc-supply = <&d3_3v>;
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};
+
+&sdhi0 {
+       pinctrl-0 = <&sdhi0_pins>;
+       pinctrl-1 = <&sdhi0_pins_uhs>;
+       pinctrl-names = "default", "state_uhs";
+
+       vmmc-supply = <&vcc_sdhi0>;
+       vqmmc-supply = <&vccq_sdhi0>;
+       cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+       wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       status = "okay";
+};
+
+&sdhi1 {
+       pinctrl-0 = <&sdhi1_pins>;
+       pinctrl-1 = <&sdhi1_pins_uhs>;
+       pinctrl-names = "default", "state_uhs";
+
+       vmmc-supply = <&vcc_sdhi1>;
+       vqmmc-supply = <&vccq_sdhi1>;
+       cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+       wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+       sd-uhs-sdr50;
+       status = "okay";
+};
+
+&i2c1 {
+       pinctrl-0 = <&i2c1_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+       clock-frequency = <400000>;
+
+       composite-in@20 {
+               compatible = "adi,adv7180";
+               reg = <0x20>;
+               remote = <&vin0>;
+
+               port {
+                       adv7180: endpoint {
+                               bus-width = <8>;
+                               remote-endpoint = <&vin0ep>;
+                       };
+               };
+       };
+};
+
+&i2c4 {
+       pinctrl-0 = <&i2c4_pins>;
+       pinctrl-names = "i2c-exio4";
+};
+
+&vin0 {
+       status = "okay";
+       pinctrl-0 = <&vin0_pins>;
+       pinctrl-names = "default";
+
+       port {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               vin0ep: endpoint {
+                       remote-endpoint = <&adv7180>;
+                       bus-width = <8>;
+               };
+       };
+};
+
+&scif2 {
+       pinctrl-0 = <&scif2_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&scif_clk {
+       clock-frequency = <14745600>;
+};
+
+&qspi {
+       pinctrl-0 = <&qspi_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       flash@0 {
+               compatible = "spansion,s25fl512s", "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <30000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+               spi-cpol;
+               spi-cpha;
+               m25p,fast-read;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "loader";
+                               reg = <0x00000000 0x00040000>;
+                               read-only;
+                       };
+                       partition@40000 {
+                               label = "system";
+                               reg = <0x00040000 0x00040000>;
+                               read-only;
+                       };
+                       partition@80000 {
+                               label = "user";
+                               reg = <0x00080000 0x03f80000>;
+                       };
+               };
+       };
+};

diff --git a/arch/arm/dts/r8a7794-silk.dts b/arch/arm/dts/r8a7794-silk.dts
new file mode 100644 (file)
index 0000000..b7d9d76
--- /dev/null
+++ b/arch/arm/dts/r8a7794-silk.dts
@@ -0,0 +1,460 @@
+/*
+ * Device Tree Source for the SILK board
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2014-2015 Renesas Solutions Corp.
+ * Copyright (C) 2014-2015 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+/*
+ * SSI-AK4643
+ *
+ * SW1: 2-1: AK4643
+ *      2-3: ADV7511
+ *
+ * This command is required before playback/capture:
+ *
+ *     amixer set "LINEOUT Mixer DACL" on
+ */
+
+/dts-v1/;
+#include "r8a7794.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       model = "SILK";
+       compatible = "renesas,silk", "renesas,r8a7794";
+
+       aliases {
+               serial0 = &scif2;
+       };
+
+       chosen {
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0 0x40000000 0 0x40000000>;
+       };
+
+       d3_3v: regulator-d3-3v {
+               compatible = "regulator-fixed";
+               regulator-name = "D3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       vcc_sdhi1: regulator-vcc-sdhi1 {
+               compatible = "regulator-fixed";
+
+               regulator-name = "SDHI1 Vcc";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       vccq_sdhi1: regulator-vccq-sdhi1 {
+               compatible = "regulator-gpio";
+
+               regulator-name = "SDHI1 VccQ";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+               gpios-states = <1>;
+               states = <3300000 1
+                         1800000 0>;
+       };
+
+       vga-encoder {
+               compatible = "adi,adv7123";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               adv7123_in: endpoint {
+                                       remote-endpoint = <&du_out_rgb1>;
+                               };
+                       };
+                       port@1 {
+                               reg = <1>;
+                               adv7123_out: endpoint {
+                                       remote-endpoint = <&vga_in>;
+                               };
+                       };
+               };
+       };
+
+       hdmi-out {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_con: endpoint {
+                               remote-endpoint = <&adv7511_out>;
+                       };
+               };
+       };
+
+       vga {
+               compatible = "vga-connector";
+
+               port {
+                       vga_in: endpoint {
+                               remote-endpoint = <&adv7123_out>;
+                       };
+               };
+       };
+
+       x2_clk: x2-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <148500000>;
+       };
+
+       x3_clk: x3-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <74250000>;
+       };
+
+       x9_clk: audio_clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <12288000>;
+       };
+
+       sound {
+               compatible = "simple-audio-card";
+
+               simple-audio-card,format = "left_j";
+               simple-audio-card,bitclock-master = <&soundcodec>;
+               simple-audio-card,frame-master = <&soundcodec>;
+
+               simple-audio-card,cpu {
+                       sound-dai = <&rcar_sound>;
+               };
+
+               soundcodec: simple-audio-card,codec {
+                       sound-dai = <&ak4643>;
+                       clocks = <&x9_clk>;
+               };
+       };
+};
+
+&extal_clk {
+       clock-frequency = <20000000>;
+};
+
+&pfc {
+       pinctrl-0 = <&scif_clk_pins>;
+       pinctrl-names = "default";
+
+       scif2_pins: scif2 {
+               groups = "scif2_data";
+               function = "scif2";
+       };
+
+       scif_clk_pins: scif_clk {
+               groups = "scif_clk";
+               function = "scif_clk";
+       };
+
+       ether_pins: ether {
+               groups = "eth_link", "eth_mdio", "eth_rmii";
+               function = "eth";
+       };
+
+       phy1_pins: phy1 {
+               groups = "intc_irq8";
+               function = "intc";
+       };
+
+       i2c1_pins: i2c1 {
+               groups = "i2c1";
+               function = "i2c1";
+       };
+
+       mmcif0_pins: mmcif0 {
+               groups = "mmc_data8", "mmc_ctrl";
+               function = "mmc";
+       };
+
+       sdhi1_pins: sd1 {
+               groups = "sdhi1_data4", "sdhi1_ctrl";
+               function = "sdhi1";
+       };
+
+       qspi_pins: qspi {
+               groups = "qspi_ctrl", "qspi_data4";
+               function = "qspi";
+       };
+
+       vin0_pins: vin0 {
+               groups = "vin0_data8", "vin0_clk";
+               function = "vin0";
+       };
+
+       usb0_pins: usb0 {
+               groups = "usb0";
+               function = "usb0";
+       };
+
+       usb1_pins: usb1 {
+               groups = "usb1";
+               function = "usb1";
+       };
+
+       du0_pins: du0 {
+               groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
+               function = "du0";
+       };
+
+       du1_pins: du1 {
+               groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
+               function = "du1";
+       };
+
+       ssi_pins: sound {
+               groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+               function = "ssi";
+       };
+
+       audio_clk_pins: audio_clk {
+               groups = "audio_clkc";
+               function = "audio_clk";
+       };
+};
+
+&scif2 {
+       pinctrl-0 = <&scif2_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&scif_clk {
+       clock-frequency = <14745600>;
+};
+
+&ether {
+       pinctrl-0 = <&ether_pins &phy1_pins>;
+       pinctrl-names = "default";
+
+       phy-handle = <&phy1>;
+       renesas,ether-link-active-low;
+       status = "okay";
+
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+               interrupt-parent = <&irqc0>;
+               interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+               micrel,led-mode = <1>;
+       };
+};
+
+&i2c1 {
+       pinctrl-0 = <&i2c1_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+       clock-frequency = <400000>;
+
+       ak4643: codec@12 {
+               compatible = "asahi-kasei,ak4643";
+               #sound-dai-cells = <0>;
+               reg = <0x12>;
+       };
+
+       composite-in@20 {
+               compatible = "adi,adv7180";
+               reg = <0x20>;
+               remote = <&vin0>;
+
+               port {
+                       adv7180: endpoint {
+                               bus-width = <8>;
+                               remote-endpoint = <&vin0ep>;
+                       };
+               };
+       };
+
+       hdmi@39 {
+               compatible = "adi,adv7511w";
+               reg = <0x39>;
+               interrupt-parent = <&gpio5>;
+               interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+
+               adi,input-depth = <8>;
+               adi,input-colorspace = "rgb";
+               adi,input-clock = "1x";
+               adi,input-style = <1>;
+               adi,input-justification = "evenly";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               adv7511_in: endpoint {
+                                       remote-endpoint = <&du_out_rgb0>;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                               adv7511_out: endpoint {
+                                       remote-endpoint = <&hdmi_con>;
+                               };
+                       };
+               };
+       };
+};
+
+&mmcif0 {
+       pinctrl-0 = <&mmcif0_pins>;
+       pinctrl-names = "default";
+
+       vmmc-supply = <&d3_3v>;
+       vqmmc-supply = <&d3_3v>;
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};
+
+&sdhi1 {
+       pinctrl-0 = <&sdhi1_pins>;
+       pinctrl-names = "default";
+
+       vmmc-supply = <&vcc_sdhi1>;
+       vqmmc-supply = <&vccq_sdhi1>;
+       cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&qspi {
+       pinctrl-0 = <&qspi_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       flash@0 {
+               compatible = "spansion,s25fl512s", "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <30000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+               spi-cpol;
+               spi-cpha;
+               m25p,fast-read;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "loader";
+                               reg = <0x00000000 0x00040000>;
+                               read-only;
+                       };
+                       partition@40000 {
+                               label = "user";
+                               reg = <0x00040000 0x00400000>;
+                               read-only;
+                       };
+                       partition@440000 {
+                               label = "flash";
+                               reg = <0x00440000 0x03bc0000>;
+                       };
+               };
+       };
+};
+
+/* composite video input */
+&vin0 {
+       status = "okay";
+       pinctrl-0 = <&vin0_pins>;
+       pinctrl-names = "default";
+
+       port {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               vin0ep: endpoint {
+                       remote-endpoint = <&adv7180>;
+                       bus-width = <8>;
+               };
+       };
+};
+
+&pci0 {
+       status = "okay";
+       pinctrl-0 = <&usb0_pins>;
+       pinctrl-names = "default";
+};
+
+&pci1 {
+       status = "okay";
+       pinctrl-0 = <&usb1_pins>;
+       pinctrl-names = "default";
+};
+
+&usbphy {
+       status = "okay";
+};
+
+&du {
+       pinctrl-0 = <&du0_pins &du1_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+                <&x2_clk>, <&x3_clk>;
+       clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
+
+       ports {
+               port@0 {
+                       endpoint {
+                               remote-endpoint = <&adv7511_in>;
+                       };
+               };
+               port@1 {
+                       endpoint {
+                               remote-endpoint = <&adv7123_in>;
+                       };
+               };
+       };
+};
+
+&rcar_sound {
+       pinctrl-0 = <&ssi_pins &audio_clk_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       /* Single DAI */
+       #sound-dai-cells = <0>;
+
+       rcar_sound,dai {
+               dai0 {
+                       playback = <&ssi0>;
+                       capture  = <&ssi1>;
+               };
+       };
+};
+
+&ssi1 {
+       shared-pin;
+};

diff --git a/arch/arm/dts/r8a7794.dtsi b/arch/arm/dts/r8a7794.dtsi
new file mode 100644 (file)
index 0000000..c17087e
--- /dev/null
+++ b/arch/arm/dts/r8a7794.dtsi
@@ -0,0 +1,1347 @@
+/*
+ * Device Tree Source for the r8a7794 SoC
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2014 Ulrich Hecht
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <dt-bindings/clock/r8a7794-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7794-sysc.h>
+
+/ {
+       compatible = "renesas,r8a7794";
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       aliases {
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &i2c4;
+               i2c5 = &i2c5;
+               i2c6 = &i2c6;
+               i2c7 = &i2c7;
+               spi0 = &qspi;
+               vin0 = &vin0;
+               vin1 = &vin1;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0>;
+                       clock-frequency = <1000000000>;
+                       clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
+                       power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
+                       next-level-cache = <&L2_CA7>;
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <1>;
+                       clock-frequency = <1000000000>;
+                       clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
+                       power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
+                       next-level-cache = <&L2_CA7>;
+               };
+
+               L2_CA7: cache-controller-0 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A7794_PD_CA7_SCU>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
+       };
+
+       gic: interrupt-controller@f1001000 {
+               compatible = "arm,gic-400";
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+               interrupt-controller;
+               reg = <0 0xf1001000 0 0x1000>,
+                       <0 0xf1002000 0 0x2000>,
+                       <0 0xf1004000 0 0x2000>,
+                       <0 0xf1006000 0 0x2000>;
+               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+               clocks = <&cpg CPG_MOD 408>;
+               clock-names = "clk";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 408>;
+       };
+
+       gpio0: gpio@e6050000 {
+               compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6050000 0 0x50>;
+               interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 0 32>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 912>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 912>;
+       };
+
+       gpio1: gpio@e6051000 {
+               compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6051000 0 0x50>;
+               interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 32 26>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 911>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 911>;
+       };
+
+       gpio2: gpio@e6052000 {
+               compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6052000 0 0x50>;
+               interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 64 32>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 910>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 910>;
+       };
+
+       gpio3: gpio@e6053000 {
+               compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6053000 0 0x50>;
+               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 96 32>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 909>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 909>;
+       };
+
+       gpio4: gpio@e6054000 {
+               compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6054000 0 0x50>;
+               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 128 32>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 908>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 908>;
+       };
+
+       gpio5: gpio@e6055000 {
+               compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6055000 0 0x50>;
+               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 160 28>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 907>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 907>;
+       };
+
+       gpio6: gpio@e6055400 {
+               compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6055400 0 0x50>;
+               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 192 26>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 905>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 905>;
+       };
+
+       cmt0: timer@ffca0000 {
+               compatible = "renesas,cmt-48-gen2";
+               reg = <0 0xffca0000 0 0x1004>;
+               interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 124>;
+               clock-names = "fck";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 124>;
+
+               renesas,channels-mask = <0x60>;
+
+               status = "disabled";
+       };
+
+       cmt1: timer@e6130000 {
+               compatible = "renesas,cmt-48-gen2";
+               reg = <0 0xe6130000 0 0x1004>;
+               interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 329>;
+               clock-names = "fck";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 329>;
+
+               renesas,channels-mask = <0xff>;
+
+               status = "disabled";
+       };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+       };
+
+       irqc0: interrupt-controller@e61c0000 {
+               compatible = "renesas,irqc-r8a7794", "renesas,irqc";
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               reg = <0 0xe61c0000 0 0x200>;
+               interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 407>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 407>;
+       };
+
+       pfc: pin-controller@e6060000 {
+               compatible = "renesas,pfc-r8a7794";
+               reg = <0 0xe6060000 0 0x11c>;
+       };
+
+       dmac0: dma-controller@e6700000 {
+               compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
+               reg = <0 0xe6700000 0 0x20000>;
+               interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "error",
+                               "ch0", "ch1", "ch2", "ch3",
+                               "ch4", "ch5", "ch6", "ch7",
+                               "ch8", "ch9", "ch10", "ch11",
+                               "ch12", "ch13", "ch14";
+               clocks = <&cpg CPG_MOD 219>;
+               clock-names = "fck";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 219>;
+               #dma-cells = <1>;
+               dma-channels = <15>;
+       };
+
+       dmac1: dma-controller@e6720000 {
+               compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
+               reg = <0 0xe6720000 0 0x20000>;
+               interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "error",
+                               "ch0", "ch1", "ch2", "ch3",
+                               "ch4", "ch5", "ch6", "ch7",
+                               "ch8", "ch9", "ch10", "ch11",
+                               "ch12", "ch13", "ch14";
+               clocks = <&cpg CPG_MOD 218>;
+               clock-names = "fck";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 218>;
+               #dma-cells = <1>;
+               dma-channels = <15>;
+       };
+
+       audma0: dma-controller@ec700000 {
+               compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
+               reg = <0 0xec700000 0 0x10000>;
+               interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "error",
+                                 "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
+                                 "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
+                                 "ch12";
+               clocks = <&cpg CPG_MOD 502>;
+               clock-names = "fck";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 502>;
+               #dma-cells = <1>;
+               dma-channels = <13>;
+       };
+
+       scifa0: serial@e6c40000 {
+               compatible = "renesas,scifa-r8a7794",
+                            "renesas,rcar-gen2-scifa", "renesas,scifa";
+               reg = <0 0xe6c40000 0 64>;
+               interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 204>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+                      <&dmac1 0x21>, <&dmac1 0x22>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 204>;
+               status = "disabled";
+       };
+
+       scifa1: serial@e6c50000 {
+               compatible = "renesas,scifa-r8a7794",
+                            "renesas,rcar-gen2-scifa", "renesas,scifa";
+               reg = <0 0xe6c50000 0 64>;
+               interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 203>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+                      <&dmac1 0x25>, <&dmac1 0x26>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 203>;
+               status = "disabled";
+       };
+
+       scifa2: serial@e6c60000 {
+               compatible = "renesas,scifa-r8a7794",
+                            "renesas,rcar-gen2-scifa", "renesas,scifa";
+               reg = <0 0xe6c60000 0 64>;
+               interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 202>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+                      <&dmac1 0x27>, <&dmac1 0x28>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 202>;
+               status = "disabled";
+       };
+
+       scifa3: serial@e6c70000 {
+               compatible = "renesas,scifa-r8a7794",
+                            "renesas,rcar-gen2-scifa", "renesas,scifa";
+               reg = <0 0xe6c70000 0 64>;
+               interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 1106>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+                      <&dmac1 0x1b>, <&dmac1 0x1c>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 1106>;
+               status = "disabled";
+       };
+
+       scifa4: serial@e6c78000 {
+               compatible = "renesas,scifa-r8a7794",
+                            "renesas,rcar-gen2-scifa", "renesas,scifa";
+               reg = <0 0xe6c78000 0 64>;
+               interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 1107>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+                      <&dmac1 0x1f>, <&dmac1 0x20>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 1107>;
+               status = "disabled";
+       };
+
+       scifa5: serial@e6c80000 {
+               compatible = "renesas,scifa-r8a7794",
+                            "renesas,rcar-gen2-scifa", "renesas,scifa";
+               reg = <0 0xe6c80000 0 64>;
+               interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 1108>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+                      <&dmac1 0x23>, <&dmac1 0x24>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 1108>;
+               status = "disabled";
+       };
+
+       scifb0: serial@e6c20000 {
+               compatible = "renesas,scifb-r8a7794",
+                            "renesas,rcar-gen2-scifb", "renesas,scifb";
+               reg = <0 0xe6c20000 0 0x100>;
+               interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 206>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+                      <&dmac1 0x3d>, <&dmac1 0x3e>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 206>;
+               status = "disabled";
+       };
+
+       scifb1: serial@e6c30000 {
+               compatible = "renesas,scifb-r8a7794",
+                            "renesas,rcar-gen2-scifb", "renesas,scifb";
+               reg = <0 0xe6c30000 0 0x100>;
+               interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 207>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+                      <&dmac1 0x19>, <&dmac1 0x1a>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 207>;
+               status = "disabled";
+       };
+
+       scifb2: serial@e6ce0000 {
+               compatible = "renesas,scifb-r8a7794",
+                            "renesas,rcar-gen2-scifb", "renesas,scifb";
+               reg = <0 0xe6ce0000 0 0x100>;
+               interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 216>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+                      <&dmac1 0x1d>, <&dmac1 0x1e>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 216>;
+               status = "disabled";
+       };
+
+       scif0: serial@e6e60000 {
+               compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+                            "renesas,scif";
+               reg = <0 0xe6e60000 0 64>;
+               interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+                      <&dmac1 0x29>, <&dmac1 0x2a>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 721>;
+               status = "disabled";
+       };
+
+       scif1: serial@e6e68000 {
+               compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+                            "renesas,scif";
+               reg = <0 0xe6e68000 0 64>;
+               interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+                      <&dmac1 0x2d>, <&dmac1 0x2e>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 720>;
+               status = "disabled";
+       };
+
+       scif2: serial@e6e58000 {
+               compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+                            "renesas,scif";
+               reg = <0 0xe6e58000 0 64>;
+               interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+                      <&dmac1 0x2b>, <&dmac1 0x2c>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 719>;
+               status = "disabled";
+       };
+
+       scif3: serial@e6ea8000 {
+               compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+                            "renesas,scif";
+               reg = <0 0xe6ea8000 0 64>;
+               interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+                      <&dmac1 0x2f>, <&dmac1 0x30>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 718>;
+               status = "disabled";
+       };
+
+       scif4: serial@e6ee0000 {
+               compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+                            "renesas,scif";
+               reg = <0 0xe6ee0000 0 64>;
+               interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+                      <&dmac1 0xfb>, <&dmac1 0xfc>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 715>;
+               status = "disabled";
+       };
+
+       scif5: serial@e6ee8000 {
+               compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
+                            "renesas,scif";
+               reg = <0 0xe6ee8000 0 64>;
+               interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+                      <&dmac1 0xfd>, <&dmac1 0xfe>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 714>;
+               status = "disabled";
+       };
+
+       hscif0: serial@e62c0000 {
+               compatible = "renesas,hscif-r8a7794",
+                            "renesas,rcar-gen2-hscif", "renesas,hscif";
+               reg = <0 0xe62c0000 0 96>;
+               interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+                      <&dmac1 0x39>, <&dmac1 0x3a>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 717>;
+               status = "disabled";
+       };
+
+       hscif1: serial@e62c8000 {
+               compatible = "renesas,hscif-r8a7794",
+                            "renesas,rcar-gen2-hscif", "renesas,hscif";
+               reg = <0 0xe62c8000 0 96>;
+               interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+                      <&dmac1 0x4d>, <&dmac1 0x4e>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 716>;
+               status = "disabled";
+       };
+
+       hscif2: serial@e62d0000 {
+               compatible = "renesas,hscif-r8a7794",
+                            "renesas,rcar-gen2-hscif", "renesas,hscif";
+               reg = <0 0xe62d0000 0 96>;
+               interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+                      <&dmac1 0x3b>, <&dmac1 0x3c>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 713>;
+               status = "disabled";
+       };
+
+       icram0: sram@e63a0000 {
+               compatible = "mmio-sram";
+               reg = <0 0xe63a0000 0 0x12000>;
+       };
+
+       icram1: sram@e63c0000 {
+               compatible = "mmio-sram";
+               reg = <0 0xe63c0000 0 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0 0xe63c0000 0x1000>;
+
+               smp-sram@0 {
+                       compatible = "renesas,smp-sram";
+                       reg = <0 0x10>;
+               };
+       };
+
+       ether: ethernet@ee700000 {
+               compatible = "renesas,ether-r8a7794";
+               reg = <0 0xee700000 0 0x400>;
+               interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 813>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 813>;
+               phy-mode = "rmii";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       avb: ethernet@e6800000 {
+               compatible = "renesas,etheravb-r8a7794",
+                            "renesas,etheravb-rcar-gen2";
+               reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+               interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 812>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 812>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       /* The memory map in the User's Manual maps the cores to bus numbers */
+       i2c0: i2c@e6508000 {
+               compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+               reg = <0 0xe6508000 0 0x40>;
+               interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 931>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 931>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               i2c-scl-internal-delay-ns = <6>;
+               status = "disabled";
+       };
+
+       i2c1: i2c@e6518000 {
+               compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+               reg = <0 0xe6518000 0 0x40>;
+               interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 930>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 930>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               i2c-scl-internal-delay-ns = <6>;
+               status = "disabled";
+       };
+
+       i2c2: i2c@e6530000 {
+               compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+               reg = <0 0xe6530000 0 0x40>;
+               interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 929>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 929>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               i2c-scl-internal-delay-ns = <6>;
+               status = "disabled";
+       };
+
+       i2c3: i2c@e6540000 {
+               compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+               reg = <0 0xe6540000 0 0x40>;
+               interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 928>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 928>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               i2c-scl-internal-delay-ns = <6>;
+               status = "disabled";
+       };
+
+       i2c4: i2c@e6520000 {
+               compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+               reg = <0 0xe6520000 0 0x40>;
+               interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 927>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 927>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               i2c-scl-internal-delay-ns = <6>;
+               status = "disabled";
+       };
+
+       i2c5: i2c@e6528000 {
+               compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
+               reg = <0 0xe6528000 0 0x40>;
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 925>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 925>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               i2c-scl-internal-delay-ns = <6>;
+               status = "disabled";
+       };
+
+       i2c6: i2c@e6500000 {
+               compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
+                            "renesas,rmobile-iic";
+               reg = <0 0xe6500000 0 0x425>;
+               interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 318>;
+               dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+                      <&dmac1 0x61>, <&dmac1 0x62>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 318>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       i2c7: i2c@e6510000 {
+               compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
+                            "renesas,rmobile-iic";
+               reg = <0 0xe6510000 0 0x425>;
+               interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 323>;
+               dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+                      <&dmac1 0x65>, <&dmac1 0x66>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 323>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       mmcif0: mmc@ee200000 {
+               compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
+               reg = <0 0xee200000 0 0x80>;
+               interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 315>;
+               dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+                      <&dmac1 0xd1>, <&dmac1 0xd2>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 315>;
+               reg-io-width = <4>;
+               status = "disabled";
+       };
+
+       sdhi0: sd@ee100000 {
+               compatible = "renesas,sdhi-r8a7794";
+               reg = <0 0xee100000 0 0x328>;
+               interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 314>;
+               dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                      <&dmac1 0xcd>, <&dmac1 0xce>;
+               dma-names = "tx", "rx", "tx", "rx";
+               max-frequency = <195000000>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 314>;
+               status = "disabled";
+       };
+
+       sdhi1: sd@ee140000 {
+               compatible = "renesas,sdhi-r8a7794";
+               reg = <0 0xee140000 0 0x100>;
+               interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 312>;
+               dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+                      <&dmac1 0xc1>, <&dmac1 0xc2>;
+               dma-names = "tx", "rx", "tx", "rx";
+               max-frequency = <97500000>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 312>;
+               status = "disabled";
+       };
+
+       sdhi2: sd@ee160000 {
+               compatible = "renesas,sdhi-r8a7794";
+               reg = <0 0xee160000 0 0x100>;
+               interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 311>;
+               dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                      <&dmac1 0xd3>, <&dmac1 0xd4>;
+               dma-names = "tx", "rx", "tx", "rx";
+               max-frequency = <97500000>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 311>;
+               status = "disabled";
+       };
+
+       qspi: spi@e6b10000 {
+               compatible = "renesas,qspi-r8a7794", "renesas,qspi";
+               reg = <0 0xe6b10000 0 0x2c>;
+               interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 917>;
+               dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                      <&dmac1 0x17>, <&dmac1 0x18>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 917>;
+               num-cs = <1>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       vin0: video@e6ef0000 {
+               compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
+               reg = <0 0xe6ef0000 0 0x1000>;
+               interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 811>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 811>;
+               status = "disabled";
+       };
+
+       vin1: video@e6ef1000 {
+               compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
+               reg = <0 0xe6ef1000 0 0x1000>;
+               interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 810>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 810>;
+               status = "disabled";
+       };
+
+       pci0: pci@ee090000 {
+               compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
+               device_type = "pci";
+               reg = <0 0xee090000 0 0xc00>,
+                     <0 0xee080000 0 0x1100>;
+               interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 703>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 703>;
+               status = "disabled";
+
+               bus-range = <0 0>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               #interrupt-cells = <1>;
+               ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+               interrupt-map-mask = <0xff00 0 0 0x7>;
+               interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+               usb@1,0 {
+                       reg = <0x800 0 0 0 0>;
+                       phys = <&usb0 0>;
+                       phy-names = "usb";
+               };
+
+               usb@2,0 {
+                       reg = <0x1000 0 0 0 0>;
+                       phys = <&usb0 0>;
+                       phy-names = "usb";
+               };
+       };
+
+       pci1: pci@ee0d0000 {
+               compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
+               device_type = "pci";
+               reg = <0 0xee0d0000 0 0xc00>,
+                     <0 0xee0c0000 0 0x1100>;
+               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 703>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 703>;
+               status = "disabled";
+
+               bus-range = <1 1>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               #interrupt-cells = <1>;
+               ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+               interrupt-map-mask = <0xff00 0 0 0x7>;
+               interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+               usb@1,0 {
+                       reg = <0x10800 0 0 0 0>;
+                       phys = <&usb2 0>;
+                       phy-names = "usb";
+               };
+
+               usb@2,0 {
+                       reg = <0x11000 0 0 0 0>;
+                       phys = <&usb2 0>;
+                       phy-names = "usb";
+               };
+       };
+
+       hsusb: usb@e6590000 {
+               compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
+               reg = <0 0xe6590000 0 0x100>;
+               interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 704>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 704>;
+               renesas,buswait = <4>;
+               phys = <&usb0 1>;
+               phy-names = "usb";
+               status = "disabled";
+       };
+
+       usbphy: usb-phy@e6590100 {
+               compatible = "renesas,usb-phy-r8a7794",
+                            "renesas,rcar-gen2-usb-phy";
+               reg = <0 0xe6590100 0 0x100>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clocks = <&cpg CPG_MOD 704>;
+               clock-names = "usbhs";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 704>;
+               status = "disabled";
+
+               usb0: usb-channel@0 {
+                       reg = <0>;
+                       #phy-cells = <1>;
+               };
+               usb2: usb-channel@2 {
+                       reg = <2>;
+                       #phy-cells = <1>;
+               };
+       };
+
+       vsp@fe928000 {
+               compatible = "renesas,vsp1";
+               reg = <0 0xfe928000 0 0x8000>;
+               interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 131>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 131>;
+       };
+
+       vsp@fe930000 {
+               compatible = "renesas,vsp1";
+               reg = <0 0xfe930000 0 0x8000>;
+               interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 128>;
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 128>;
+       };
+
+       du: display@feb00000 {
+               compatible = "renesas,du-r8a7794";
+               reg = <0 0xfeb00000 0 0x40000>;
+               reg-names = "du";
+               interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
+               clock-names = "du.0", "du.1";
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               du_out_rgb0: endpoint {
+                               };
+                       };
+                       port@1 {
+                               reg = <1>;
+                               du_out_rgb1: endpoint {
+                               };
+                       };
+               };
+       };
+
+       can0: can@e6e80000 {
+               compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
+               reg = <0 0xe6e80000 0 0x1000>;
+               interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
+                        <&can_clk>;
+               clock-names = "clkp1", "clkp2", "can_clk";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 916>;
+               status = "disabled";
+       };
+
+       can1: can@e6e88000 {
+               compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
+               reg = <0 0xe6e88000 0 0x1000>;
+               interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
+                        <&can_clk>;
+               clock-names = "clkp1", "clkp2", "can_clk";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 915>;
+               status = "disabled";
+       };
+
+       /* External root clock */
+       extal_clk: extal {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board. */
+               clock-frequency = <0>;
+       };
+
+       /* External USB clock - can be overridden by the board */
+       usb_extal_clk: usb_extal {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <48000000>;
+       };
+
+       /* External CAN clock */
+       can_clk: can {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board. */
+               clock-frequency = <0>;
+       };
+
+       /* External SCIF clock */
+       scif_clk: scif {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board. */
+               clock-frequency = <0>;
+       };
+
+       /*
+        * The external audio clocks are configured  as 0 Hz fixed
+        * frequency clocks by default.  Boards that provide audio
+        * clocks should override them.
+        */
+       audio_clka: audio_clka {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+       audio_clkb: audio_clkb {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+       audio_clkc: audio_clkc {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
+       cpg: clock-controller@e6150000 {
+               compatible = "renesas,r8a7794-cpg-mssr";
+               reg = <0 0xe6150000 0 0x1000>;
+               clocks = <&extal_clk>, <&usb_extal_clk>;
+               clock-names = "extal", "usb_extal";
+               #clock-cells = <2>;
+               #power-domain-cells = <0>;
+               #reset-cells = <1>;
+       };
+
+       rst: reset-controller@e6160000 {
+               compatible = "renesas,r8a7794-rst";
+               reg = <0 0xe6160000 0 0x0100>;
+       };
+
+       prr: chipid@ff000044 {
+               compatible = "renesas,prr";
+               reg = <0 0xff000044 0 4>;
+       };
+
+       sysc: system-controller@e6180000 {
+               compatible = "renesas,r8a7794-sysc";
+               reg = <0 0xe6180000 0 0x0200>;
+               #power-domain-cells = <1>;
+       };
+
+       ipmmu_sy0: mmu@e6280000 {
+               compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+               reg = <0 0xe6280000 0 0x1000>;
+               interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               status = "disabled";
+       };
+
+       ipmmu_sy1: mmu@e6290000 {
+               compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+               reg = <0 0xe6290000 0 0x1000>;
+               interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               status = "disabled";
+       };
+
+       ipmmu_ds: mmu@e6740000 {
+               compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+               reg = <0 0xe6740000 0 0x1000>;
+               interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               status = "disabled";
+       };
+
+       ipmmu_mp: mmu@ec680000 {
+               compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+               reg = <0 0xec680000 0 0x1000>;
+               interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               status = "disabled";
+       };
+
+       ipmmu_mx: mmu@fe951000 {
+               compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+               reg = <0 0xfe951000 0 0x1000>;
+               interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               status = "disabled";
+       };
+
+       ipmmu_gp: mmu@e62a0000 {
+               compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
+               reg = <0 0xe62a0000 0 0x1000>;
+               interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               status = "disabled";
+       };
+
+       rcar_sound: sound@ec500000 {
+               /*
+                * #sound-dai-cells is required
+                *
+                * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+                * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+                */
+               compatible = "renesas,rcar_sound-r8a7794",
+                            "renesas,rcar_sound-gen2";
+               reg =   <0 0xec500000 0 0x1000>, /* SCU */
+                       <0 0xec5a0000 0 0x100>,  /* ADG */
+                       <0 0xec540000 0 0x1000>, /* SSIU */
+                       <0 0xec541000 0 0x280>,  /* SSI */
+                       <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
+               reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+               clocks = <&cpg CPG_MOD 1005>,
+                        <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+                        <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+                        <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+                        <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+                        <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+                        <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
+                        <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
+                        <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
+                        <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+                        <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+                        <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+                        <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
+                        <&cpg CPG_CORE R8A7794_CLK_M2>;
+               clock-names = "ssi-all",
+                             "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+                             "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+                             "src.6", "src.5", "src.4", "src.3", "src.2",
+                             "src.1",
+                             "ctu.0", "ctu.1",
+                             "mix.0", "mix.1",
+                             "dvc.0", "dvc.1",
+                             "clk_a", "clk_b", "clk_c", "clk_i";
+               power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+               resets = <&cpg 1005>,
+                        <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
+                        <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
+                        <&cpg 1014>, <&cpg 1015>;
+               reset-names = "ssi-all",
+                             "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+                             "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+
+               status = "disabled";
+
+               rcar_sound,dvc {
+                       dvc0: dvc-0 {
+                               dmas = <&audma0 0xbc>;
+                               dma-names = "tx";
+                       };
+                       dvc1: dvc-1 {
+                               dmas = <&audma0 0xbe>;
+                               dma-names = "tx";
+                       };
+               };
+
+               rcar_sound,mix {
+                       mix0: mix-0 { };
+                       mix1: mix-1 { };
+               };
+
+               rcar_sound,ctu {
+                       ctu00: ctu-0 { };
+                       ctu01: ctu-1 { };
+                       ctu02: ctu-2 { };
+                       ctu03: ctu-3 { };
+                       ctu10: ctu-4 { };
+                       ctu11: ctu-5 { };
+                       ctu12: ctu-6 { };
+                       ctu13: ctu-7 { };
+               };
+
+               rcar_sound,src {
+                       src-0 {
+                               status = "disabled";
+                       };
+                       src1: src-1 {
+                               interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x87>, <&audma0 0x9c>;
+                               dma-names = "rx", "tx";
+                       };
+                       src2: src-2 {
+                               interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x89>, <&audma0 0x9e>;
+                               dma-names = "rx", "tx";
+                       };
+                       src3: src-3 {
+                               interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x8b>, <&audma0 0xa0>;
+                               dma-names = "rx", "tx";
+                       };
+                       src4: src-4 {
+                               interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x8d>, <&audma0 0xb0>;
+                               dma-names = "rx", "tx";
+                       };
+                       src5: src-5 {
+                               interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x8f>, <&audma0 0xb2>;
+                               dma-names = "rx", "tx";
+                       };
+                       src6: src-6 {
+                               interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x91>, <&audma0 0xb4>;
+                               dma-names = "rx", "tx";
+                       };
+               };
+
+               rcar_sound,ssi {
+                       ssi0: ssi-0 {
+                               interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x01>, <&audma0 0x02>,
+                                      <&audma0 0x15>, <&audma0 0x16>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi1: ssi-1 {
+                               interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x03>, <&audma0 0x04>,
+                                      <&audma0 0x49>, <&audma0 0x4a>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi2: ssi-2 {
+                               interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x05>, <&audma0 0x06>,
+                                      <&audma0 0x63>, <&audma0 0x64>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi3: ssi-3 {
+                               interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x07>, <&audma0 0x08>,
+                                      <&audma0 0x6f>, <&audma0 0x70>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi4: ssi-4 {
+                               interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x09>, <&audma0 0x0a>,
+                                      <&audma0 0x71>, <&audma0 0x72>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi5: ssi-5 {
+                               interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x0b>, <&audma0 0x0c>,
+                                      <&audma0 0x73>, <&audma0 0x74>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi6: ssi-6 {
+                               interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x0d>, <&audma0 0x0e>,
+                                      <&audma0 0x75>, <&audma0 0x76>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi7: ssi-7 {
+                               interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x0f>, <&audma0 0x10>,
+                                      <&audma0 0x79>, <&audma0 0x7a>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi8: ssi-8 {
+                               interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x11>, <&audma0 0x12>,
+                                      <&audma0 0x7b>, <&audma0 0x7c>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi9: ssi-9 {
+                               interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x13>, <&audma0 0x14>,
+                                      <&audma0 0x7d>, <&audma0 0x7e>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+               };
+       };
+};

diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
new file mode 100644 (file)
index 0000000..93e99c3
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_H__
+
+/* CPG */
+#define R8A7794_CLK_MAIN               0
+#define R8A7794_CLK_PLL0               1
+#define R8A7794_CLK_PLL1               2
+#define R8A7794_CLK_PLL3               3
+#define R8A7794_CLK_LB                 4
+#define R8A7794_CLK_QSPI               5
+#define R8A7794_CLK_SDH                        6
+#define R8A7794_CLK_SD0                        7
+#define R8A7794_CLK_RCAN               8
+
+/* MSTP0 */
+#define R8A7794_CLK_MSIOF0             0
+
+/* MSTP1 */
+#define R8A7794_CLK_VCP0               1
+#define R8A7794_CLK_VPC0               3
+#define R8A7794_CLK_TMU1               11
+#define R8A7794_CLK_3DG                        12
+#define R8A7794_CLK_2DDMAC             15
+#define R8A7794_CLK_FDP1_0             19
+#define R8A7794_CLK_TMU3               21
+#define R8A7794_CLK_TMU2               22
+#define R8A7794_CLK_CMT0               24
+#define R8A7794_CLK_TMU0               25
+#define R8A7794_CLK_VSP1_DU0           28
+#define R8A7794_CLK_VSP1_S             31
+
+/* MSTP2 */
+#define R8A7794_CLK_SCIFA2             2
+#define R8A7794_CLK_SCIFA1             3
+#define R8A7794_CLK_SCIFA0             4
+#define R8A7794_CLK_MSIOF2             5
+#define R8A7794_CLK_SCIFB0             6
+#define R8A7794_CLK_SCIFB1             7
+#define R8A7794_CLK_MSIOF1             8
+#define R8A7794_CLK_SCIFB2             16
+#define R8A7794_CLK_SYS_DMAC1          18
+#define R8A7794_CLK_SYS_DMAC0          19
+
+/* MSTP3 */
+#define R8A7794_CLK_SDHI2              11
+#define R8A7794_CLK_SDHI1              12
+#define R8A7794_CLK_SDHI0              14
+#define R8A7794_CLK_MMCIF0             15
+#define R8A7794_CLK_IIC0               18
+#define R8A7794_CLK_IIC1               23
+#define R8A7794_CLK_CMT1               29
+#define R8A7794_CLK_USBDMAC0           30
+#define R8A7794_CLK_USBDMAC1           31
+
+/* MSTP4 */
+#define R8A7794_CLK_IRQC               7
+#define R8A7794_CLK_INTC_SYS           8
+
+/* MSTP5 */
+#define R8A7794_CLK_AUDIO_DMAC0                2
+#define R8A7794_CLK_PWM                        23
+
+/* MSTP7 */
+#define R8A7794_CLK_EHCI               3
+#define R8A7794_CLK_HSUSB              4
+#define R8A7794_CLK_HSCIF2             13
+#define R8A7794_CLK_SCIF5              14
+#define R8A7794_CLK_SCIF4              15
+#define R8A7794_CLK_HSCIF1             16
+#define R8A7794_CLK_HSCIF0             17
+#define R8A7794_CLK_SCIF3              18
+#define R8A7794_CLK_SCIF2              19
+#define R8A7794_CLK_SCIF1              20
+#define R8A7794_CLK_SCIF0              21
+#define R8A7794_CLK_DU1                        23
+#define R8A7794_CLK_DU0                        24
+
+/* MSTP8 */
+#define R8A7794_CLK_VIN1               10
+#define R8A7794_CLK_VIN0               11
+#define R8A7794_CLK_ETHERAVB           12
+#define R8A7794_CLK_ETHER              13
+
+/* MSTP9 */
+#define R8A7794_CLK_GPIO6              5
+#define R8A7794_CLK_GPIO5              7
+#define R8A7794_CLK_GPIO4              8
+#define R8A7794_CLK_GPIO3              9
+#define R8A7794_CLK_GPIO2              10
+#define R8A7794_CLK_GPIO1              11
+#define R8A7794_CLK_GPIO0              12
+#define R8A7794_CLK_RCAN1              15
+#define R8A7794_CLK_RCAN0              16
+#define R8A7794_CLK_QSPI_MOD           17
+#define R8A7794_CLK_I2C5               25
+#define R8A7794_CLK_I2C4               27
+#define R8A7794_CLK_I2C3               28
+#define R8A7794_CLK_I2C2               29
+#define R8A7794_CLK_I2C1               30
+#define R8A7794_CLK_I2C0               31
+
+/* MSTP10 */
+#define R8A7794_CLK_SSI_ALL            5
+#define R8A7794_CLK_SSI9               6
+#define R8A7794_CLK_SSI8               7
+#define R8A7794_CLK_SSI7               8
+#define R8A7794_CLK_SSI6               9
+#define R8A7794_CLK_SSI5               10
+#define R8A7794_CLK_SSI4               11
+#define R8A7794_CLK_SSI3               12
+#define R8A7794_CLK_SSI2               13
+#define R8A7794_CLK_SSI1               14
+#define R8A7794_CLK_SSI0               15
+#define R8A7794_CLK_SCU_ALL            17
+#define R8A7794_CLK_SCU_DVC1           18
+#define R8A7794_CLK_SCU_DVC0           19
+#define R8A7794_CLK_SCU_CTU1_MIX1      20
+#define R8A7794_CLK_SCU_CTU0_MIX0      21
+#define R8A7794_CLK_SCU_SRC6           25
+#define R8A7794_CLK_SCU_SRC5           26
+#define R8A7794_CLK_SCU_SRC4           27
+#define R8A7794_CLK_SCU_SRC3           28
+#define R8A7794_CLK_SCU_SRC2           29
+#define R8A7794_CLK_SCU_SRC1           30
+
+/* MSTP11 */
+#define R8A7794_CLK_SCIFA3             6
+#define R8A7794_CLK_SCIFA4             7
+#define R8A7794_CLK_SCIFA5             8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */

diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
new file mode 100644 (file)
index 0000000..9d72031
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7794 CPG Core Clocks */
+#define R8A7794_CLK_Z2                 0
+#define R8A7794_CLK_ZG                 1
+#define R8A7794_CLK_ZTR                        2
+#define R8A7794_CLK_ZTRD2              3
+#define R8A7794_CLK_ZT                 4
+#define R8A7794_CLK_ZX                 5
+#define R8A7794_CLK_ZS                 6
+#define R8A7794_CLK_HP                 7
+#define R8A7794_CLK_I                  8
+#define R8A7794_CLK_B                  9
+#define R8A7794_CLK_LB                 10
+#define R8A7794_CLK_P                  11
+#define R8A7794_CLK_CL                 12
+#define R8A7794_CLK_CP                 13
+#define R8A7794_CLK_M2                 14
+#define R8A7794_CLK_ADSP               15
+#define R8A7794_CLK_ZB3                        16
+#define R8A7794_CLK_ZB3D2              17
+#define R8A7794_CLK_DDR                        18
+#define R8A7794_CLK_SDH                        19
+#define R8A7794_CLK_SD0                        20
+#define R8A7794_CLK_SD2                        21
+#define R8A7794_CLK_SD3                        22
+#define R8A7794_CLK_MMC0               23
+#define R8A7794_CLK_MP                 24
+#define R8A7794_CLK_QSPI               25
+#define R8A7794_CLK_CPEX               26
+#define R8A7794_CLK_RCAN               27
+#define R8A7794_CLK_R                  28
+#define R8A7794_CLK_OSC                        29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */

diff --git a/include/dt-bindings/power/r8a7794-sysc.h b/include/dt-bindings/power/r8a7794-sysc.h
new file mode 100644 (file)
index 0000000..862241c
--- /dev/null
+++ b/include/dt-bindings/power/r8a7794-sysc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7794_PD_CA7_CPU0             5
+#define R8A7794_PD_CA7_CPU1             6
+#define R8A7794_PD_SH_4A               16
+#define R8A7794_PD_SGX                 20
+#define R8A7794_PD_CA7_SCU             21
+
+/* Always-on power area */
+#define R8A7794_PD_ALWAYS_ON           32
+
+#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */