sunxi: Support PSCI ops on Allwinner H3

H3 has the same power sequencing procedure as the A31/A31s, which
includes the power clamps.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 4ff46e4fc0b9c1a9020d605ac6f7dbcd407b6439..90b5bfd35947ed599fad2b6f9e0c4bfb49de8073 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -106,7 +106,7 @@ psci_fiq_enter:
        str     r10, [r8, #0x100]
        timer_wait r10, ONE_MS
 
-#ifdef CONFIG_MACH_SUN6I
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
        @ Activate power clamp
        lsl     r12, r9, #2             @ x4
        add     r12, r12, r8
@@ -170,7 +170,7 @@ psci_cpu_on:
        movw    r0, #(SUNXI_PRCM_BASE & 0xffff)
        movt    r0, #(SUNXI_PRCM_BASE >> 16)
 
-#ifdef CONFIG_MACH_SUN6I
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
        @ Release power clamp
        lsl     r5, r1, #2      @ 1 register per CPU
        add     r5, r5, r0      @ PRCM