ARM: AM33xx+: Update ioregs to pass different values

Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: Tom Rini <trini@ti.com>

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 5b0454c3eab661bfaa1daab184d5c1b591a6d45a..255f333b692bb1e0ac66b8ae5e8b3965264acc84 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -88,6 +88,9 @@ void config_ddr_phy(const struct emif_regs *regs, int nr)
  */
 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 {
+       if (!cmd)
+               return;
+
        writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
        writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 
@@ -105,6 +108,9 @@ void config_ddr_data(const struct ddr_data *data, int nr)
 {
        int i;
 
+       if (!data)
+               return;
+
        for (i = 0; i < DDR_DATA_REGS_NR; i++) {
                writel(data->datardsratio0,
                        &(ddr_data_reg[nr]+i)->dt0rdsratio0);
@@ -121,11 +127,20 @@ void config_ddr_data(const struct ddr_data *data, int nr)
        }
 }
 
-void config_io_ctrl(unsigned long val)
+void config_io_ctrl(const struct ctrl_ioregs *ioregs)
 {
-       writel(val, &ioctrl_reg->cm0ioctl);
-       writel(val, &ioctrl_reg->cm1ioctl);
-       writel(val, &ioctrl_reg->cm2ioctl);
-       writel(val, &ioctrl_reg->dt0ioctl);
-       writel(val, &ioctrl_reg->dt1ioctl);
+       if (!ioregs)
+               return;
+
+       writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
+       writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
+       writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
+       writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
+       writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
+#ifdef CONFIG_AM43XX
+       writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
+       writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
+       writel(ioregs->emif_sdram_config_ext,
+              &ioctrl_reg->emif_sdram_config_ext);
+#endif
 }

diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 59ad25c5b093a30a3b799b69ba878a464678ea90..adda650fe8d2cffce2d49cebf150ee5d614657d5 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -87,7 +87,7 @@ void __weak ddr_pll_config(unsigned int ddrpll_m)
 {
 }
 
-void config_ddr(unsigned int pll, unsigned int ioctrl,
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
                const struct ddr_data *data, const struct cmd_control *ctrl,
                const struct emif_regs *regs, int nr)
 {
@@ -99,12 +99,11 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
 
        config_ddr_data(data, nr);
 #ifdef CONFIG_AM33XX
-       config_io_ctrl(ioctrl);
+       config_io_ctrl(ioregs);
 
        /* Set CKE to be controlled by EMIF/DDR PHY */
        writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 #endif
-
        /* Program EMIF instance */
        config_ddr_phy(regs, nr);
        set_sdram_timings(regs, nr);

diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c
index 99f3a869bbca2f6aa717c584c49061a12ae1c315..b3b150a577ad00a1cb742f07e980c1888281c70a 100644 (file)
--- a/board/compulab/cm_t335/spl.c
+++ b/board/compulab/cm_t335/spl.c
@@ -20,6 +20,14 @@
 #include <asm/arch/hardware_am33xx.h>
 #include <asm/sizes.h>
 
+const struct ctrl_ioregs ioregs = {
+       .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
+       .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
+       .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
+       .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
+       .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
+};
+
 static const struct ddr_data ddr3_data = {
        .datardsratio0          = MT41J128MJT125_RD_DQS,
        .datawdsratio0          = MT41J128MJT125_WR_DQS,
@@ -89,7 +97,7 @@ static void probe_sdram_size(long size)
                reset_cpu(0);
        }
        debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
-       config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
+       config_ddr(303, &ioregs, &ddr3_data,
                   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 }
 

diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 6a8ca2b4c39ba90e02dd81db10e3c20aa1f74dd8..089a835e0c6cfe671e39df73ed81b4afaebaeed5 100644 (file)
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -77,9 +77,17 @@ void set_mux_conf_regs(void)
        enable_board_pin_mux();
 }
 
+const struct ctrl_ioregs ioregs = {
+       .cm0ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
+       .cm1ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
+       .cm2ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
+       .dt0ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
+       .dt1ioctl               = K4B2G1646EBIH9_IOCTRL_VALUE,
+};
+
 void sdram_init(void)
 {
-       config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+       config_ddr(400, &ioregs, &ddr3_data,
                   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 }
 #endif

diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 68463e78dbfd2859c3b340d90f4ff5b85f8f23cd..7e5e07ff232a6834a36ae63a6f60338ce69eddd7 100644 (file)
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -50,6 +50,14 @@ const struct dpll_params *get_dpll_ddr_params(void)
 }
 
 #ifdef CONFIG_REV1
+const struct ctrl_ioregs ioregs = {
+       .cm0ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
+       .cm1ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
+       .cm2ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
+       .dt0ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
+       .dt1ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
+};
+
 static const struct ddr_data ddr3_data = {
        .datardsratio0 = MT41J256M8HX15E_RD_DQS,
        .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
@@ -81,10 +89,18 @@ static struct emif_regs ddr3_emif_reg_data = {
 
 void sdram_init(void)
 {
-       config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
+       config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
                   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 }
 #else
+const struct ctrl_ioregs ioregs = {
+       .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
 static const struct ddr_data ddr3_data = {
        .datardsratio0 = MT41K256M16HA125E_RD_DQS,
        .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
@@ -116,7 +132,7 @@ static struct emif_regs ddr3_emif_reg_data = {
 
 void sdram_init(void)
 {
-       config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data,
+       config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
                   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 }
 #endif

diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c
index 3a5e11dc816d7fc107de7252262ab06ac2d4d2a1..6c316faa8f1aad9d9fd62c49aeb855c7ec7113f3 100644 (file)
--- a/board/siemens/dxr2/board.c
+++ b/board/siemens/dxr2/board.c
@@ -144,6 +144,10 @@ struct ddr_data dxr2_ddr3_data = {
 
 struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
 };
+
+struct ctrl_ioregs dxr2_ddr3_ioregs = {
+};
+
        /* pass values from eeprom */
        dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
        dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
@@ -165,7 +169,13 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
        dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
        dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 
-       config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data,
+       dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
+       dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
+       dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
+       dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
+       dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
+
+       config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
                   &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
 }
 

diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index 0a25b4b40cc7d417c0df811c3618528ecbc733b0..ef3d6cc158d71d16221654bc057c2be1f943ca56 100644 (file)
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -69,7 +69,15 @@ struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
        .cmd2iclkout = 0,
 };
 
-       config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
+const struct ctrl_ioregs ioregs = {
+       .cm0ioctl               = DXR2_IOCTRL_VAL,
+       .cm1ioctl               = DXR2_IOCTRL_VAL,
+       .cm2ioctl               = DXR2_IOCTRL_VAL,
+       .dt0ioctl               = DXR2_IOCTRL_VAL,
+       .dt1ioctl               = DXR2_IOCTRL_VAL,
+};
+
+       config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
                   &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
 }
 

diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index 77592dbba886946ade6c977d24d3bfedd86aa9a2..25ab54d9a2a5142f0d6bbf1d1122c15a0dd8d16f 100644 (file)
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -74,7 +74,15 @@ struct cmd_control rut_ddr3_cmd_ctrl_data = {
        .cmd2iclkout = 1,
 };
 
-       config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
+const struct ctrl_ioregs ioregs = {
+       .cm0ioctl               = RUT_IOCTRL_VAL,
+       .cm1ioctl               = RUT_IOCTRL_VAL,
+       .cm2ioctl               = RUT_IOCTRL_VAL,
+       .dt0ioctl               = RUT_IOCTRL_VAL,
+       .dt1ioctl               = RUT_IOCTRL_VAL,
+};
+
+       config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
                   &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
 }
 

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 33693e4ead50b6429a05877432b427a11daa3946..57217688d635e40d7fb500348cc4a85a1d53e889 100644 (file)
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -426,6 +426,38 @@ void set_mux_conf_regs(void)
        enable_board_pin_mux(&header);
 }
 
+const struct ctrl_ioregs ioregs_evmsk = {
+       .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
+       .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
+       .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
+       .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
+       .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_bonelt = {
+       .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+       .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_evm15 = {
+       .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
+       .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
+       .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
+       .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
+       .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs = {
+       .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
+       .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
+       .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
+       .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
+       .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
 void sdram_init(void)
 {
        __maybe_unused struct am335x_baseboard_id header;
@@ -443,18 +475,18 @@ void sdram_init(void)
        }
 
        if (board_is_evm_sk(&header))
-               config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
+               config_ddr(303, &ioregs_evmsk, &ddr3_data,
                           &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
        else if (board_is_bone_lt(&header))
-               config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
+               config_ddr(400, &ioregs_bonelt,
                           &ddr3_beagleblack_data,
                           &ddr3_beagleblack_cmd_ctrl_data,
                           &ddr3_beagleblack_emif_reg_data, 0);
        else if (board_is_evm_15_or_later(&header))
-               config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
+               config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
                           &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
        else
-               config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
+               config_ddr(266, &ioregs, &ddr2_data,
                           &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 }
 #endif

diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 0b76a7790598849fe4d858bc7c3d7b6ccdc26805..140ad7103ad2ad5e19b16a9ea1255a0fba617d4a 100644 (file)
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -95,9 +95,9 @@ void sdram_init(void)
 {
        config_dmm(&evm_lisa_map_regs);
 
-       config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+       config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
                   &evm_ddr2_emif0_regs, 0);
-       config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+       config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
                   &evm_ddr2_emif1_regs, 1);
 }
 #endif

diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
index a53859e52e4a923c639aebfaba937648ad73474b..b6bf16236f408aadc2003fcc880a747c608c5f6f 100644 (file)
--- a/board/ti/ti816x/evm.c
+++ b/board/ti/ti816x/evm.c
@@ -191,22 +191,26 @@ void sdram_init(void)
        if (CONFIG_TI816X_USE_EMIF0) {
                ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
                        (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
-               config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0);
+               config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
+                          0);
        }
 
        if (CONFIG_TI816X_USE_EMIF1) {
                ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
                        (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
-               config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1);
+               config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
+                          1);
        }
 #endif
 
 #ifdef CONFIG_TI816X_EVM_DDR3
        if (CONFIG_TI816X_USE_EMIF0)
-               config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);
+               config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
+                          0);
 
        if (CONFIG_TI816X_USE_EMIF1)
-               config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1);
+               config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
+                          1);
 #endif
 }
 #endif /* CONFIG_SPL_BUILD */