pico-imx6: Add splashscreen support

Add splashscreen support. Tested with the parallel
FT5x06-WVGA panel.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>

diff --git a/board/technexion/pico-imx6/pico-imx6.c b/board/technexion/pico-imx6/pico-imx6.c
index 2ae5af83d2f50892f148d92dbab0c8457d6abc61..f8eeb40555bc71d8c426bcce759a34c85f47cd5f 100644 (file)
--- a/board/technexion/pico-imx6/pico-imx6.c
+++ b/board/technexion/pico-imx6/pico-imx6.c
@@ -13,6 +13,8 @@
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/mach-imx/video.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
@@ -31,6 +33,8 @@ DECLARE_GLOBAL_DATA_PTR;
        PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
 #define ETH_PHY_RESET          IMX_GPIO_NR(1, 26)
+#define LVDS0_EN               IMX_GPIO_NR(2, 8)
+#define LVDS0_BL_EN            IMX_GPIO_NR(2, 9)
 
 int dram_init(void)
 {
@@ -49,6 +53,15 @@ static void setup_iomux_uart(void)
        SETUP_IOMUX_PADS(uart1_pads);
 }
 
+static iomux_v3_cfg_t const lvds_pads[] = {
+       /* lvds */
+       IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+       IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
 static iomux_v3_cfg_t const enet_pads[] = {
        IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
        IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
@@ -82,10 +95,207 @@ static void setup_iomux_enet(void)
        gpio_set_value(ETH_PHY_RESET, 1);
 }
 
+#if defined(CONFIG_VIDEO_IPUV3)
+static iomux_v3_cfg_t const ft5x06_wvga_pads[] = {
+       IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+       IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
+       IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
+       IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
+       IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
+       IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
+       IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
+       IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
+       IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
+       IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
+       IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
+       IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
+       IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
+       IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
+       IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
+       IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
+       IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
+       IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
+       IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
+       IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
+       IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
+       IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
+       IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
+       IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18),
+       IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19),
+       IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20),
+       IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21),
+       IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22),
+       IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23),
+       IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
+       IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+       imx_enable_hdmi_phy();
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+       struct iomuxc *iomux = (struct iomuxc *)
+                               IOMUXC_BASE_ADDR;
+
+       /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
+       u32 reg = readl(&iomux->gpr[2]);
+       reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+       writel(reg, &iomux->gpr[2]);
+
+       /* Enable Backlight - use GPIO for Brightness adjustment */
+       SETUP_IOMUX_PAD(PAD_SD4_DAT1__GPIO2_IO09);
+       gpio_request(IMX_GPIO_NR(2, 9), "backlight_enable");
+       gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+
+       gpio_request(IMX_GPIO_NR(2, 8), "brightness");
+       SETUP_IOMUX_PAD(PAD_SD4_DAT0__GPIO2_IO08);
+       gpio_direction_output(IMX_GPIO_NR(2, 8), 1);
+}
+
+static void enable_ft5x06_wvga(struct display_info_t const *dev)
+{
+       SETUP_IOMUX_PADS(ft5x06_wvga_pads);
+
+       gpio_request(IMX_GPIO_NR(2, 10), "parallel_enable");
+       gpio_request(IMX_GPIO_NR(2, 11), "parallel_brightness");
+       gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
+       gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
+}
+
+struct display_info_t const displays[] = {{
+       .bus    = 1,
+       .addr   = 0x38,
+       .pixfmt = IPU_PIX_FMT_RGB24,
+       .detect = NULL,
+       .enable = enable_ft5x06_wvga,
+       .mode   = {
+               .name           = "FT5x06-WVGA",
+               .refresh        = 60,
+               .xres           = 800,
+               .yres           = 480,
+               .pixclock       = 30303,
+               .left_margin    = 45,
+               .right_margin   = 210,
+               .upper_margin   = 22,
+               .lower_margin   = 22,
+               .hsync_len      = 1,
+               .vsync_len      = 1,
+               .sync           = 0,
+               .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = -1,
+       .addr   = 0,
+       .pixfmt = IPU_PIX_FMT_RGB24,
+       .detect = NULL,
+       .enable = enable_lvds,
+       .mode   = {
+               .name           = "hj070na",
+               .refresh        = 60,
+               .xres           = 1024,
+               .yres           = 600,
+               .pixclock       = 15385,
+               .left_margin    = 220,
+               .right_margin   = 40,
+               .upper_margin   = 21,
+               .lower_margin   = 7,
+               .hsync_len      = 60,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = -1,
+       .addr   = 0,
+       .pixfmt = IPU_PIX_FMT_RGB24,
+       .detect = detect_hdmi,
+       .enable = do_enable_hdmi,
+       .mode   = {
+               .name           = "HDMI",
+               .refresh        = 60,
+               .xres           = 1024,
+               .yres           = 768,
+               .pixclock       = 15385,
+               .left_margin    = 220,
+               .right_margin   = 40,
+               .upper_margin   = 21,
+               .lower_margin   = 7,
+               .hsync_len      = 60,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+       int reg;
+
+       /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
+       SETUP_IOMUX_PADS(lvds_pads);
+       gpio_request(LVDS0_EN, "lvds0_enable");
+       gpio_request(LVDS0_BL_EN, "lvds0_bl_enable");
+       gpio_direction_output(LVDS0_EN, 1);
+       gpio_direction_output(LVDS0_BL_EN, 1);
+
+       enable_ipu_clock();
+       imx_setup_hdmi();
+
+       reg = __raw_readl(&mxc_ccm->CCGR3);
+       reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+       writel(reg, &mxc_ccm->CCGR3);
+
+       /* set LDB0, LDB1 clk select to 011/011 */
+       reg = readl(&mxc_ccm->cs2cdr);
+       reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+               | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+       reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+                | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+       writel(reg, &mxc_ccm->cs2cdr);
+
+       reg = readl(&mxc_ccm->cscmr2);
+       reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+       writel(reg, &mxc_ccm->cscmr2);
+
+       reg = readl(&mxc_ccm->chsccdr);
+       reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+               << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+       reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+               << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+       writel(reg, &mxc_ccm->chsccdr);
+
+        reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
+               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+               | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+               | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
+               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+               | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
+               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+       writel(reg, &iomux->gpr[2]);
+       reg = readl(&iomux->gpr[3]);
+
+       reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+               | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+               | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+               << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+
+       writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();
 
+#if defined(CONFIG_VIDEO_IPUV3)
+       setup_display();
+#endif
+
        return 0;
 }
 

diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig
index 4291f6fab06b65e26106c2907d3f1b45dd4a602d..02787f8250eadc92ec40bf383d703d88a698d34f 100644 (file)
--- a/configs/pico-imx6_defconfig
+++ b/configs/pico-imx6_defconfig
@@ -69,3 +69,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IPUV3=y

diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
index d539b88bf778401b49e65ce6b72501352a5d96ef..467d5ff4f59b10e174a2f83ad1ada3c3490c8c92 100644 (file)
--- a/include/configs/pico-imx6.h
+++ b/include/configs/pico-imx6.h
@@ -139,4 +139,14 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
+/* Framebuffer */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
 #endif                        /* __CONFIG_H * */