#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
- "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+ "clock-frequency", CFG_SYS_NS16550_CLK, 1);
#endif
sysclk_path = fdt_get_alias(blob, "sysclk");
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "fsl,ns16550",
- "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+ "clock-frequency", CFG_SYS_NS16550_CLK, 1);
#endif
do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
/* uArchitecture specifics */
/* Serial Info */
-#define CONFIG_SYS_NS16550_CLK 100000000
-#define CONFIG_SYS_NS16550_CLK_DIV 54
-#define CONFIG_SYS_NS16550_COM3 0x18023000
+#define CFG_SYS_NS16550_CLK 100000000
+#define CFG_SYS_NS16550_CLK_DIV 54
+#define CFG_SYS_NS16550_COM3 0x18023000
#endif /* __ARCH_CONFIGS_H */
/* uArchitecture specifics */
/* Serial Info */
-#define CONFIG_SYS_NS16550_CLK 0x03b9aca0
-#define CONFIG_SYS_NS16550_COM1 0x18000300
+#define CFG_SYS_NS16550_CLK 0x03b9aca0
+#define CFG_SYS_NS16550_COM1 0x18000300
#endif /* __ARCH_CONFIGS_H */
#define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
+#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
+#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#endif
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
#define CFG_SYS_FSL_TIMER_ADDR 0x023e0000
#define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \
#endif
#endif
-#if !defined(CONFIG_SYS_NS16550_CLK)
-#define CONFIG_SYS_NS16550_CLK 13000000
+#if !defined(CFG_SYS_NS16550_CLK)
+#define CFG_SYS_NS16550_CLK 13000000
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_FSL_SEC_OFFSET 0x00700000
board_gpio_init();
#if !CONFIG_IS_ENABLED(DM_SERIAL)
- ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM1),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+ ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM1),
+ CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
#endif
/*
* Fix Power and Emulation Management Register
*/
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
-#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
+#if (CFG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
&davinci_uart0_ctrl_regs->pwremu_mgmt);
#else
&davinci_uart2_ctrl_regs->pwremu_mgmt);
void putc(char c)
{
if (c == '\n')
- ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), '\r');
+ ns16550_putc((struct ns16550 *)(CFG_SYS_NS16550_COM1), '\r');
- ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), c);
+ ns16550_putc((struct ns16550 *)(CFG_SYS_NS16550_COM1), c);
}
#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
* driver doesn't handle this.
*/
#ifndef CONFIG_DM_SERIAL
- ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM2),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+ ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM2),
+ CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
#endif
return 0;
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct ns16550_plat lpc32xx_uart[] = {
{ .base = UART3_BASE, .reg_shift = 2,
- .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+ .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = UART4_BASE, .reg_shift = 2,
- .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+ .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = UART5_BASE, .reg_shift = 2,
- .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+ .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = UART6_BASE, .reg_shift = 2,
- .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+ .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
};
#if defined(CONFIG_LPC32XX_HSUART)
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct ns16550_plat am33xx_serial[] = {
- { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
- .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-# ifdef CONFIG_SYS_NS16550_COM2
- { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
- .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
-# ifdef CONFIG_SYS_NS16550_COM3
- { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
- .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
- { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
- .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
- { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
- .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
- { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
- .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+ { .base = CFG_SYS_NS16550_COM1, .reg_shift = 2,
+ .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+# ifdef CFG_SYS_NS16550_COM2
+ { .base = CFG_SYS_NS16550_COM2, .reg_shift = 2,
+ .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+# ifdef CFG_SYS_NS16550_COM3
+ { .base = CFG_SYS_NS16550_COM3, .reg_shift = 2,
+ .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+ { .base = CFG_SYS_NS16550_COM4, .reg_shift = 2,
+ .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+ { .base = CFG_SYS_NS16550_COM5, .reg_shift = 2,
+ .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
+ { .base = CFG_SYS_NS16550_COM6, .reg_shift = 2,
+ .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
# endif
# endif
};
U_BOOT_DRVINFOS(am33xx_uarts) = {
{ "ns16550_serial", &am33xx_serial[0] },
-# ifdef CONFIG_SYS_NS16550_COM2
+# ifdef CFG_SYS_NS16550_COM2
{ "ns16550_serial", &am33xx_serial[1] },
-# ifdef CONFIG_SYS_NS16550_COM3
+# ifdef CFG_SYS_NS16550_COM3
{ "ns16550_serial", &am33xx_serial[2] },
{ "ns16550_serial", &am33xx_serial[3] },
{ "ns16550_serial", &am33xx_serial[4] },
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static struct ns16550_plat ns16550_com1_pdata = {
- .base = CONFIG_SYS_NS16550_COM1,
+ .base = CFG_SYS_NS16550_COM1,
.reg_shift = 2,
- .clock = CONFIG_SYS_NS16550_CLK,
+ .clock = CFG_SYS_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "ns16550",
- "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+ "clock-frequency", CFG_SYS_NS16550_CLK, 1);
#endif
#ifdef CONFIG_FSL_CORENET
* This function compares several CONFIG_xxx macros that contain physical
* addresses with the corresponding nodes in the device tree, to see if
* the physical addresses are all correct. For example, if
- * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
+ * CFG_SYS_NS16550_COM1 is defined, then it contains the virtual address
* of the first UART. We convert this to a physical address and compare
* that with the physical address of the first ns16550-compatible node
* in the device tree. If they don't match, then we display a warning.
*/
aliases = fdt_path_offset(fdt, "/aliases");
if (aliases > 0) {
-#ifdef CONFIG_SYS_NS16550_COM1
+#ifdef CFG_SYS_NS16550_COM1
if (!fdt_verify_alias_address(fdt, aliases, "serial0",
- CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
+ CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM1)))
return 0;
#endif
-#ifdef CONFIG_SYS_NS16550_COM2
+#ifdef CFG_SYS_NS16550_COM2
if (!fdt_verify_alias_address(fdt, aliases, "serial1",
- CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
+ CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM2)))
return 0;
#endif
}
* TODO: Convert this to a clock driver exists that can give us the UART
* clock here.
*/
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#define CFG_SYS_NS16550_CLK get_serial_clock()
#endif
#endif /* _ASM_CONFIG_H_ */
#include <ns16550.h>
#define SOFTWARE_SHUTDOWN 0x31
#define SOFTWARE_REBOOT 0x43
-#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
+#define CFG_SYS_NS16550_COM2 KW_UART1_BASE
void reset_misc(void)
{
int b_d;
printf("Synology reset...");
udelay(50000);
- b_d = ns16550_calc_divisor((struct ns16550 *)CONFIG_SYS_NS16550_COM2,
- CONFIG_SYS_NS16550_CLK, 9600);
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM2, b_d);
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM2,
+ b_d = ns16550_calc_divisor((struct ns16550 *)CFG_SYS_NS16550_COM2,
+ CFG_SYS_NS16550_CLK, 9600);
+ ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM2, b_d);
+ ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM2,
SOFTWARE_REBOOT);
}
void enable_uart_pin_mux(u32 addr)
{
switch (addr) {
- case CONFIG_SYS_NS16550_COM1:
+ case CFG_SYS_NS16550_COM1:
enable_uart0_pin_mux();
break;
- case CONFIG_SYS_NS16550_COM2:
+ case CFG_SYS_NS16550_COM2:
enable_uart1_pin_mux();
break;
- case CONFIG_SYS_NS16550_COM3:
+ case CFG_SYS_NS16550_COM3:
enable_uart2_pin_mux();
break;
- case CONFIG_SYS_NS16550_COM4:
+ case CFG_SYS_NS16550_COM4:
enable_uart3_pin_mux();
break;
- case CONFIG_SYS_NS16550_COM5:
+ case CFG_SYS_NS16550_COM5:
enable_uart4_pin_mux();
break;
- case CONFIG_SYS_NS16550_COM6:
+ case CFG_SYS_NS16550_COM6:
enable_uart5_pin_mux();
break;
}
return get_fdt_virt();
}
-/* See CONFIG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */
+/* See CFG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */
int get_serial_clock(void)
{
return get_bus_freq(0);
int nodeoff;
nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
- CONFIG_SYS_NS16550_COM2);
+ CFG_SYS_NS16550_COM2);
if (nodeoff > 0) {
fdt_status_disabled(blob, nodeoff);
plat_ratio >>= 1;
gd->bus_clk = get_board_sys_clk() * plat_ratio;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+ ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
#ifdef CONFIG_SPL_MMC_BOOT
plat_ratio >>= 1;
gd->bus_clk = get_board_sys_clk() * plat_ratio;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+ ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
void putc(char c)
{
if (c == '\n')
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r');
+ ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r');
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c);
+ ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c);
}
void puts(const char *str)
bus_clk = get_board_sys_clk() * plat_ratio;
gd->bus_clk = bus_clk;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+ ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
bus_clk / 16 / CONFIG_BAUDRATE);
#ifdef CONFIG_SPL_MMC_BOOT
puts("\nSD boot...\n");
plat_ratio >>= 1;
gd->bus_clk = get_board_sys_clk() * plat_ratio;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+ ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
void putc(char c)
{
if (c == '\n')
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r');
+ ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r');
- ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c);
+ ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c);
}
void puts(const char *str)
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+ ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
ccb_clk / 16 / CONFIG_BAUDRATE);
#if defined(CONFIG_SPL_MMC_BOOT)
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
uart_clk = sys_clk * plat_ratio / 2;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+ ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
uart_clk / 16 / CONFIG_BAUDRATE);
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+ ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
ccb_clk / 16 / CONFIG_BAUDRATE);
#if defined(CONFIG_SPL_MMC_BOOT)
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+ ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
ccb_clk / 16 / CONFIG_BAUDRATE);
#if defined(CONFIG_SPL_MMC_BOOT)
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+ ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
ccb_clk / 16 / CONFIG_BAUDRATE);
puts("\nSD boot...\n");
};
static const struct ns16550_plat rx51_serial = {
- .base = CONFIG_SYS_NS16550_COM3,
+ .base = CFG_SYS_NS16550_COM3,
.reg_shift = 2,
- .clock = CONFIG_SYS_NS16550_CLK,
+ .clock = CFG_SYS_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
Support NS16550 UART or compatible. This can be enabled in the
device tree with the correct input clock frequency. If the input
clock frequency is not defined in the device tree, the macro
- CONFIG_SYS_NS16550_CLK defined in a legacy board header file will
+ CFG_SYS_NS16550_CLK defined in a legacy board header file will
be used. It can be a constant or a function to get clock, eg,
get_serial_clock().
#if CONFIG_IS_ENABLED(DM_SERIAL)
-#ifndef CONFIG_SYS_NS16550_CLK
-#define CONFIG_SYS_NS16550_CLK 0
+#ifndef CFG_SYS_NS16550_CLK
+#define CFG_SYS_NS16550_CLK 0
#endif
/*
if (!plat->clock)
plat->clock = dev_read_u32_default(dev, "clock-frequency",
- CONFIG_SYS_NS16550_CLK);
+ CFG_SYS_NS16550_CLK);
if (!plat->clock)
- plat->clock = CONFIG_SYS_NS16550_CLK;
+ plat->clock = CFG_SYS_NS16550_CLK;
if (!plat->clock) {
debug("ns16550 clock not defined\n");
return -EINVAL;
#define DECLARE_HSUART_PRIV(port) \
static struct mtk_serial_priv mtk_hsuart##port = { \
- .regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \
- .fixed_clk_rate = CONFIG_SYS_NS16550_CLK \
+ .regs = (struct mtk_serial_regs *)CFG_SYS_NS16550_COM##port, \
+ .fixed_clk_rate = CFG_SYS_NS16550_CLK \
};
#define DECLARE_HSUART_FUNCTIONS(port) \
#error "Invalid console index value."
#endif
-#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
+#if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1)
#error "Console port 1 defined but not configured."
-#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
+#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2)
#error "Console port 2 defined but not configured."
-#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
+#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3)
#error "Console port 3 defined but not configured."
-#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
+#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4)
#error "Console port 4 defined but not configured."
-#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
+#elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5)
#error "Console port 5 defined but not configured."
-#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
+#elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6)
#error "Console port 6 defined but not configured."
#endif
-#if defined(CONFIG_SYS_NS16550_COM1)
+#if defined(CFG_SYS_NS16550_COM1)
DECLARE_HSUART(1, "mtk-hsuart0");
#endif
-#if defined(CONFIG_SYS_NS16550_COM2)
+#if defined(CFG_SYS_NS16550_COM2)
DECLARE_HSUART(2, "mtk-hsuart1");
#endif
-#if defined(CONFIG_SYS_NS16550_COM3)
+#if defined(CFG_SYS_NS16550_COM3)
DECLARE_HSUART(3, "mtk-hsuart2");
#endif
-#if defined(CONFIG_SYS_NS16550_COM4)
+#if defined(CFG_SYS_NS16550_COM4)
DECLARE_HSUART(4, "mtk-hsuart3");
#endif
-#if defined(CONFIG_SYS_NS16550_COM5)
+#if defined(CFG_SYS_NS16550_COM5)
DECLARE_HSUART(5, "mtk-hsuart4");
#endif
-#if defined(CONFIG_SYS_NS16550_COM6)
+#if defined(CFG_SYS_NS16550_COM6)
DECLARE_HSUART(6, "mtk-hsuart5");
#endif
void mtk_serial_initialize(void)
{
-#if defined(CONFIG_SYS_NS16550_COM1)
+#if defined(CFG_SYS_NS16550_COM1)
serial_register(&mtk_hsuart1_device);
#endif
-#if defined(CONFIG_SYS_NS16550_COM2)
+#if defined(CFG_SYS_NS16550_COM2)
serial_register(&mtk_hsuart2_device);
#endif
-#if defined(CONFIG_SYS_NS16550_COM3)
+#if defined(CFG_SYS_NS16550_COM3)
serial_register(&mtk_hsuart3_device);
#endif
-#if defined(CONFIG_SYS_NS16550_COM4)
+#if defined(CFG_SYS_NS16550_COM4)
serial_register(&mtk_hsuart4_device);
#endif
-#if defined(CONFIG_SYS_NS16550_COM5)
+#if defined(CFG_SYS_NS16550_COM5)
serial_register(&mtk_hsuart5_device);
#endif
-#if defined(CONFIG_SYS_NS16550_COM6)
+#if defined(CFG_SYS_NS16550_COM6)
serial_register(&mtk_hsuart6_device);
#endif
}
#error "Invalid console index value."
#endif
-#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
+#if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1)
#error "Console port 1 defined but not configured."
-#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
+#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2)
#error "Console port 2 defined but not configured."
-#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
+#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3)
#error "Console port 3 defined but not configured."
-#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
+#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4)
#error "Console port 4 defined but not configured."
-#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
+#elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5)
#error "Console port 5 defined but not configured."
-#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
+#elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6)
#error "Console port 6 defined but not configured."
#endif
* the array is 0 based.
*/
static struct ns16550 *serial_ports[6] = {
-#ifdef CONFIG_SYS_NS16550_COM1
- (struct ns16550 *)CONFIG_SYS_NS16550_COM1,
+#ifdef CFG_SYS_NS16550_COM1
+ (struct ns16550 *)CFG_SYS_NS16550_COM1,
#else
NULL,
#endif
-#ifdef CONFIG_SYS_NS16550_COM2
- (struct ns16550 *)CONFIG_SYS_NS16550_COM2,
+#ifdef CFG_SYS_NS16550_COM2
+ (struct ns16550 *)CFG_SYS_NS16550_COM2,
#else
NULL,
#endif
-#ifdef CONFIG_SYS_NS16550_COM3
- (struct ns16550 *)CONFIG_SYS_NS16550_COM3,
+#ifdef CFG_SYS_NS16550_COM3
+ (struct ns16550 *)CFG_SYS_NS16550_COM3,
#else
NULL,
#endif
-#ifdef CONFIG_SYS_NS16550_COM4
- (struct ns16550 *)CONFIG_SYS_NS16550_COM4,
+#ifdef CFG_SYS_NS16550_COM4
+ (struct ns16550 *)CFG_SYS_NS16550_COM4,
#else
NULL,
#endif
-#ifdef CONFIG_SYS_NS16550_COM5
- (struct ns16550 *)CONFIG_SYS_NS16550_COM5,
+#ifdef CFG_SYS_NS16550_COM5
+ (struct ns16550 *)CFG_SYS_NS16550_COM5,
#else
NULL,
#endif
-#ifdef CONFIG_SYS_NS16550_COM6
- (struct ns16550 *)CONFIG_SYS_NS16550_COM6
+#ifdef CFG_SYS_NS16550_COM6
+ (struct ns16550 *)CFG_SYS_NS16550_COM6
#else
NULL
#endif
{ \
int clock_divisor; \
clock_divisor = ns16550_calc_divisor(serial_ports[port-1], \
- CONFIG_SYS_NS16550_CLK, gd->baudrate); \
+ CFG_SYS_NS16550_CLK, gd->baudrate); \
ns16550_init(serial_ports[port - 1], clock_divisor); \
return 0 ; \
} \
{
int clock_divisor;
- clock_divisor = ns16550_calc_divisor(PORT, CONFIG_SYS_NS16550_CLK,
+ clock_divisor = ns16550_calc_divisor(PORT, CFG_SYS_NS16550_CLK,
gd->baudrate);
ns16550_reinit(PORT, clock_divisor);
}
_serial_setbrg(dev_index);
}
-#if defined(CONFIG_SYS_NS16550_COM1)
+#if defined(CFG_SYS_NS16550_COM1)
DECLARE_ESERIAL_FUNCTIONS(1);
struct serial_device eserial1_device =
INIT_ESERIAL_STRUCTURE(1, "eserial0");
#endif
-#if defined(CONFIG_SYS_NS16550_COM2)
+#if defined(CFG_SYS_NS16550_COM2)
DECLARE_ESERIAL_FUNCTIONS(2);
struct serial_device eserial2_device =
INIT_ESERIAL_STRUCTURE(2, "eserial1");
#endif
-#if defined(CONFIG_SYS_NS16550_COM3)
+#if defined(CFG_SYS_NS16550_COM3)
DECLARE_ESERIAL_FUNCTIONS(3);
struct serial_device eserial3_device =
INIT_ESERIAL_STRUCTURE(3, "eserial2");
#endif
-#if defined(CONFIG_SYS_NS16550_COM4)
+#if defined(CFG_SYS_NS16550_COM4)
DECLARE_ESERIAL_FUNCTIONS(4);
struct serial_device eserial4_device =
INIT_ESERIAL_STRUCTURE(4, "eserial3");
#endif
-#if defined(CONFIG_SYS_NS16550_COM5)
+#if defined(CFG_SYS_NS16550_COM5)
DECLARE_ESERIAL_FUNCTIONS(5);
struct serial_device eserial5_device =
INIT_ESERIAL_STRUCTURE(5, "eserial4");
#endif
-#if defined(CONFIG_SYS_NS16550_COM6)
+#if defined(CFG_SYS_NS16550_COM6)
DECLARE_ESERIAL_FUNCTIONS(6);
struct serial_device eserial6_device =
INIT_ESERIAL_STRUCTURE(6, "eserial5");
void ns16550_serial_initialize(void)
{
-#if defined(CONFIG_SYS_NS16550_COM1)
+#if defined(CFG_SYS_NS16550_COM1)
serial_register(&eserial1_device);
#endif
-#if defined(CONFIG_SYS_NS16550_COM2)
+#if defined(CFG_SYS_NS16550_COM2)
serial_register(&eserial2_device);
#endif
-#if defined(CONFIG_SYS_NS16550_COM3)
+#if defined(CFG_SYS_NS16550_COM3)
serial_register(&eserial3_device);
#endif
-#if defined(CONFIG_SYS_NS16550_COM4)
+#if defined(CFG_SYS_NS16550_COM4)
serial_register(&eserial4_device);
#endif
-#if defined(CONFIG_SYS_NS16550_COM5)
+#if defined(CFG_SYS_NS16550_COM5)
serial_register(&eserial5_device);
#endif
-#if defined(CONFIG_SYS_NS16550_COM6)
+#if defined(CFG_SYS_NS16550_COM6)
serial_register(&eserial6_device);
#endif
}
#include <clk.h>
#include <linux/err.h>
-#ifndef CONFIG_SYS_NS16550_CLK
-#define CONFIG_SYS_NS16550_CLK 0
+#ifndef CFG_SYS_NS16550_CLK
+#define CFG_SYS_NS16550_CLK 0
#endif
#ifdef CONFIG_DEBUG_UART_OMAP
if (!plat->clock)
plat->clock = dev_read_u32_default(dev, "clock-frequency",
- CONFIG_SYS_NS16550_CLK);
+ CFG_SYS_NS16550_CLK);
if (!plat->clock) {
debug("omap serial clock not defined\n");
return -EINVAL;
/*
* Serial Port
*/
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CFG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
/* SERDES */
#define CONFIG_FSL_SERDES
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CFG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/*
* I2C
/* Serial Port */
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CFG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* I2C */
#define I2C_PCA9557_ADDR1 0x18
* open - index 2
* shorted - index 1
*/
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_COM1 KW_UART0_BASE
/*
* Serial Port configuration
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_COM1 KW_UART0_BASE
/*
* Serial Port configuration
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
* open - index 2
* shorted - index 1
*/
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
/*
* Serial Port
*/
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/*
* I2C
/*
* Serial Port
*/
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/*
* I2C
* open - index 2
* shorted - index 1
*/
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* I2C */
#endif
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
-#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
-#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
-#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
+#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* PMIC support */
#define CONFIG_POWER_TPS65910
#define CONSOLE_COLOR_RED 0x001F
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
-#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
-#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
-#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#ifdef CONFIG_MTD_RAW_NAND
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
"echo WARNING: Could not determine device tree to use; fi; \0"
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
/* Ethernet support */
#endif /* Regular Boot */
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
-#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
-#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
-#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#endif /* ! __CONFIG_AM335X_SHC_H */
BOOTENV
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
-#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
-#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
-#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
+#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* PMIC support */
#define CONFIG_POWER_TPS65910
#include <asm/arch/omap.h>
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_CLK 48000000
+#define CFG_SYS_NS16550_CLK 48000000
/* I2C Configuration */
#define V_SCLK (V_OSCK)
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
+#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#ifndef CONFIG_SPL_BUILD
/* USB Device Firmware Update support */
#define CONFIG_IODELAY_RECALIBRATION
-#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
+#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
+#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
+#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
#define CONFIG_SYS_OMAP_ABE_SYSCK
/*
* Serial Port
*/
-#define CONFIG_SYS_NS16550_CLK 25000000
+#define CFG_SYS_NS16550_CLK 25000000
/* Miscellaneous configurable options */
/*
* Serial Port
*/
-#define CONFIG_SYS_NS16550_CLK 25000000
+#define CFG_SYS_NS16550_CLK 25000000
/* Miscellaneous configurable options */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define FDT_MODULE "apalis-v1.2"
#define FDT_MODULE_V1_0 "apalis"
* Apalis UART4: NVIDIA UARTC
*/
#define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define UBOOT_UPDATE \
"uboot_hwpart=1\0" \
/*
* Serial console configuration
*/
-#define CONFIG_SYS_NS16550_CLK 19660800
+#define CFG_SYS_NS16550_CLK 19660800
/* Init Stack Pointer */
/*
* UART configuration
*/
-#define CONFIG_SYS_NS16550_CLK 33333333
+#define CFG_SYS_NS16550_CLK 33333333
/*
* Ethernet PHY configuration
/*DFUARGS*/
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
-#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
-#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
-#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
+#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* PMIC support */
#define CONFIG_POWER_TPS65910
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_NS16550_COM1 0xf040c000
+#define CFG_SYS_NS16550_COM1 0xf040c000
#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_NS16550_COM1 0xf040ab00
+#define CFG_SYS_NS16550_COM1 0xf040ab00
#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000
/* 12MB Malloc size */
/* console configuration */
-#define CONFIG_SYS_NS16550_CLK 25000000
+#define CFG_SYS_NS16550_CLK 25000000
/*
* Increase max uncompressed/gunzip size, keeping size same as EMMC linux
*/
#define V_NS16550_CLK 81000000
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CFG_SYS_NS16550_CLK V_NS16550_CLK
/*
* Serial console configuration.
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* SPI */
#define CONFIG_TEGRA_SLINK_CTRLS 6
/* legacy #defines for non DM bur-board */
#ifndef CONFIG_DM
-#define CONFIG_SYS_NS16550_CLK (48000000)
-#define CONFIG_SYS_NS16550_COM1 0x44e09000
+#define CFG_SYS_NS16550_CLK (48000000)
+#define CFG_SYS_NS16550_COM1 0x44e09000
#endif /* CONFIG_DM */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* SPI */
#define CONFIG_TEGRA_SLINK_CTRLS 6
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTD
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* SPI */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
NANDARGS
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
-#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
-#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
-#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
-#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
-#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* SPL */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* NS16550-ish UARTs */
-#define CONFIG_SYS_NS16550_CLK 48000000
+#define CFG_SYS_NS16550_CLK 48000000
/* Ethernet: davicom DM9000 */
#define CONFIG_DM9000_BASE 0xb6000000
#include <asm/arch/omap.h>
/* Serial support */
-#define CONFIG_SYS_NS16550_CLK 48000000
-#define CONFIG_SYS_NS16550_COM1 0x44e09000
+#define CFG_SYS_NS16550_CLK 48000000
+#define CFG_SYS_NS16550_COM1 0x44e09000
/* NAND support */
#define CFG_SYS_NAND_ECCSIZE 512
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_TEGRA_UARTA_SDIO1
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* NAND support */
* Colibri UART-C: NVIDIA UARTB
*/
#define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define UBOOT_UPDATE \
"uboot_hwpart=1\0" \
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTD
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
#elif (CONFIG_CONS_INDEX == 3)
#define CONSOLEDEV "ttyS2"
#endif
-#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
+#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
+#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
+#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
#define CONFIG_SYS_OMAP_ABE_SYSCK
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
-#define CONFIG_SYS_NS16550_CLK 40000000
-#define CONFIG_SYS_NS16550_COM1 0xb0000c00
+#define CFG_SYS_NS16550_CLK 40000000
+#define CFG_SYS_NS16550_COM1 0xb0000c00
#endif
/* UART */
#define CONFIG_TEGRA_ENABLE_UARTD
/* UARTD: keyboard satellite board UART, default */
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#ifdef CONFIG_TEGRA_ENABLE_UARTA
/* UARTA: debug board UART */
-#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE
#endif
/* NAND support */
/*
* UART configuration
*/
-#define CONFIG_SYS_NS16550_CLK 33330000
+#define CFG_SYS_NS16550_CLK 33330000
/*
* Ethernet PHY configuration
/*
* UART configuration
*/
-#define CONFIG_SYS_NS16550_CLK 33330000
+#define CFG_SYS_NS16550_CLK 33330000
/*
* Ethernet PHY configuration
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTD
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
/*
* Serial Port
*/
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#define CFG_SYS_NS16550_CLK get_serial_clock()
/*
* I2C
* Retain non-DM serial port for debug purposes.
*/
#if !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
+#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
#endif
#ifndef __ASSEMBLY__
#define CONFIG_MALLOC_F_ADDR CFG_SYS_FSL_OCRAM_BASE
/* serial port */
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
/* SPL */
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
-#define CONFIG_SYS_NS16550_CLK 40000000
-#define CONFIG_SYS_NS16550_COM3 0xb0000e00
+#define CFG_SYS_NS16550_CLK 40000000
+#define CFG_SYS_NS16550_COM3 0xb0000e00
#endif
/* GPIO */
-#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
+#define CFG_SYS_NS16550_CLK (get_serial_clock())
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
/*
* Serial Port
*/
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#define CFG_SYS_NS16550_CLK get_serial_clock()
/*
* I2C
* Serial Port
*/
#ifndef CONFIG_LPUART
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#define CFG_SYS_NS16550_CLK get_serial_clock()
#endif
/*
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* Serial Port */
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#define CFG_SYS_NS16550_CLK get_serial_clock()
/* I2C */
* Serial Port
*/
#ifndef CONFIG_LPUART
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#define CFG_SYS_NS16550_CLK get_serial_clock()
#endif
/*
/* I2C */
/* Serial Port */
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
/* Miscellaneous configurable options */
#define CPU_RELEASE_ADDR secondary_boot_addr
/* Serial Port */
-#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
+#define CFG_SYS_NS16550_CLK (get_serial_clock())
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CPU_RELEASE_ADDR secondary_boot_addr
/* Serial Port */
-#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
+#define CFG_SYS_NS16550_CLK (get_serial_clock())
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
/* Serial Port */
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
/*
* During booting, IFC is mapped at the region of 0x30000000.
/* I2C */
/* Serial Port */
-#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
+#define CFG_SYS_NS16550_CLK (get_serial_clock())
/*
* During booting, IFC is mapped at the region of 0x30000000.
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
-#define CONFIG_SYS_NS16550_CLK 50000000
-#define CONFIG_SYS_NS16550_COM1 0xbe000c00
+#define CFG_SYS_NS16550_CLK 50000000
+#define CFG_SYS_NS16550_COM1 0xbe000c00
#endif
/* Serial common */
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
-#define CONFIG_SYS_NS16550_CLK 40000000
-#define CONFIG_SYS_NS16550_COM1 0xb0000c00
+#define CFG_SYS_NS16550_CLK 40000000
+#define CFG_SYS_NS16550_COM1 0xb0000c00
#endif
/* Serial common */
#include <linux/sizes.h>
-#define CONFIG_SYS_NS16550_COM1 0x11005200
-#define CONFIG_SYS_NS16550_CLK 26000000
+#define CFG_SYS_NS16550_COM1 0x11005200
+#define CFG_SYS_NS16550_CLK 26000000
/* Environment settings */
#include <config_distro_bootcmd.h>
#include <linux/sizes.h>
-#define CONFIG_SYS_NS16550_COM1 0x11005000
-#define CONFIG_SYS_NS16550_CLK 26000000
+#define CFG_SYS_NS16550_COM1 0x11005000
+#define CFG_SYS_NS16550_CLK 26000000
/* Environment settings */
#include <config_distro_bootcmd.h>
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#if !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
+#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
#endif
#if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE)
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CFG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* SPI */
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
#include <configs/ti_omap5_common.h>
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+#define CFG_SYS_NS16550_COM3 UART3_BASE
/* MMC ENV related defines */
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
* shorted - index 1
*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CFG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* I2C */
#if !CONFIG_IS_ENABLED(DM_I2C)
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
"\0"
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1 UART0_BASE
-#define CONFIG_SYS_NS16550_COM2 UART1_BASE
-#define CONFIG_SYS_NS16550_COM3 UART2_BASE
-#define CONFIG_SYS_NS16550_COM4 UART3_BASE
-#define CONFIG_SYS_NS16550_COM5 UART4_BASE
-#define CONFIG_SYS_NS16550_COM6 UART5_BASE
+#define CFG_SYS_NS16550_COM1 UART0_BASE
+#define CFG_SYS_NS16550_COM2 UART1_BASE
+#define CFG_SYS_NS16550_COM3 UART2_BASE
+#define CFG_SYS_NS16550_COM4 UART3_BASE
+#define CFG_SYS_NS16550_COM5 UART4_BASE
+#define CFG_SYS_NS16550_COM6 UART5_BASE
#endif /* ! __CONFIG_PDU001_H */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTD
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_CLK (48000000)
-#define CONFIG_SYS_NS16550_COM1 0x44e09000
-#define CONFIG_SYS_NS16550_COM4 0x481a6000
+#define CFG_SYS_NS16550_CLK (48000000)
+#define CFG_SYS_NS16550_COM1 0x44e09000
+#define CFG_SYS_NS16550_COM4 0x481a6000
/* I2C Configuration */
* Serial
*/
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CFG_SYS_NS16550_CLK V_NS16550_CLK
+#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \
115200 }
/*
* Serial / UART configurations
*/
-#define CONFIG_SYS_NS16550_CLK 100000000
+#define CFG_SYS_NS16550_CLK 100000000
/*
* SDMMC configurations
/* ns16550 reg in the low bits of cpu reg */
#ifdef CONFIG_MACH_SUNIV
/* suniv doesn't have apb2 and uart is connected to apb1 */
-#define CONFIG_SYS_NS16550_CLK 100000000
+#define CFG_SYS_NS16550_CLK 100000000
#else
-#define CONFIG_SYS_NS16550_CLK 24000000
+#define CFG_SYS_NS16550_CLK 24000000
#endif
#ifndef CONFIG_DM_SERIAL
-# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
-# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
-# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
-# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
-# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
+# define CFG_SYS_NS16550_COM1 SUNXI_UART0_BASE
+# define CFG_SYS_NS16550_COM2 SUNXI_UART1_BASE
+# define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE
+# define CFG_SYS_NS16550_COM4 SUNXI_UART3_BASE
+# define CFG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
#endif
/* CPU */
/*
* UART configuration
*/
-#define CONFIG_SYS_NS16550_CLK 166666666
+#define CFG_SYS_NS16550_CLK 166666666
/*
* Even though the board houses Realtek RTL8211E PHY
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTD
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CFG_SYS_NS16550_CLK V_NS16550_CLK
#ifdef CONFIG_ARM64
#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
#define CONFIG_SYS_TIMERBASE 0x4802E000
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_CLK (48000000)
-#define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */
+#define CFG_SYS_NS16550_CLK (48000000)
+#define CFG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */
/* CPU */
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550_CLK (48000000)
-#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
+#define CFG_SYS_NS16550_CLK (48000000)
+#define CFG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
/* allow overwriting serial config and ethaddr */
#include <asm/arch/omap.h>
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_CLK 48000000
+#define CFG_SYS_NS16550_CLK 48000000
/*
* SPL related defines. The Public RAM memory map the ROM defines the
#define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END)
/* UART Configuration */
-#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
+#define CFG_SYS_NS16550_COM1 KS2_UART0_BASE
+#define CFG_SYS_NS16550_COM2 KS2_UART1_BASE
#ifndef CONFIG_SOC_K2G
-#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6)
+#define CFG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6)
#else
-#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2
+#define CFG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2
#endif
/* SPI Configuration */
/* NS16550 Configuration */
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CFG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
/* Select serial console configuration */
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CFG_SYS_NS16550_COM1 OMAP34XX_UART1
+#define CFG_SYS_NS16550_COM2 OMAP34XX_UART2
+#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
#endif
/* Physical Memory Map */
/*
* Hardware drivers
*/
-#define CONFIG_SYS_NS16550_CLK 48000000
+#define CFG_SYS_NS16550_CLK 48000000
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+#define CFG_SYS_NS16550_COM3 UART3_BASE
#endif
/* TWL6030 */
/*
* Hardware drivers
*/
-#define CONFIG_SYS_NS16550_CLK 48000000
+#define CFG_SYS_NS16550_CLK 48000000
/*
* Environment setup
/*
* Serial Port
*/
-#define CONFIG_SYS_NS16550_CLK 40000000
+#define CFG_SYS_NS16550_CLK 40000000
/*
* Command
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_TEGRA_UARTA_GPU
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* SPI */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
+#define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTD
-#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_SYS_UBOOT_BASE 0
/* Serial SPL */
-#define CONFIG_SYS_NS16550_CLK 40000000
-#define CONFIG_SYS_NS16550_COM3 0xb0000e00
+#define CFG_SYS_NS16550_CLK 40000000
+#define CFG_SYS_NS16550_COM3 0xb0000e00
/* RAM */
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#if !defined(CONFIG_DM_SERIAL)
-#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
+#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
#endif
/*
/* Serial Driver Info */
/*====================*/
-#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
+#define CFG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
-#define CONFIG_SYS_NS16550_CLK get_board_sys_clk()
+#define CFG_SYS_NS16550_CLK get_board_sys_clk()
/*======================*/
/* Ethernet Driver Info */
projects / u-boot.git / commitdiff
