ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs

Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.

Also adding the DDR pad io settings required for
OMAP543X SOCs here.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 7992b3fcc5d8af102ae9163080287f65bca4e079..faf5effd7313a0dd668e7cd81ec9b3b80a23264c 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -473,6 +473,16 @@ const struct ctrl_ioregs ioregs_omap5432_es1 = {
        .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 };
 
+const struct ctrl_ioregs ioregs_omap5432_es2 = {
+       .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
+       .ctrl_lpddr2ch = 0x0,
+       .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
+       .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
+       .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
+       .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
+       .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+};
+
 void hw_data_init(void)
 {
        u32 omap_rev = omap_revision();
@@ -506,11 +516,15 @@ void get_ioregs(const struct ctrl_ioregs **regs)
 
        switch (omap_rev) {
        case OMAP5430_ES1_0:
+       case OMAP5430_ES2_0:
                *regs = &ioregs_omap5430;
        break;
        case OMAP5432_ES1_0:
                *regs = &ioregs_omap5432_es1;
        break;
+       case OMAP5432_ES2_0:
+               *regs = &ioregs_omap5432_es2;
+       break;
 
        default:
                printf("\n INVALID OMAP REVISION ");

diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 687800facc2d91eac41ac6199326fe3afb14beab..2ef7fcdf4c68f4bcf33ac4418f792332feb6ee5d 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -67,6 +67,25 @@ const struct emif_regs emif_regs_532_mhz_2cs = {
        .emif_ddr_ext_phy_ctrl_5        = 0x04010040
 };
 
+const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
+       .sdram_config_init              = 0x80800EBA,
+       .sdram_config                   = 0x808022BA,
+       .ref_ctrl                       = 0x0000081A,
+       .sdram_tim1                     = 0x772F6873,
+       .sdram_tim2                     = 0x304a129a,
+       .sdram_tim3                     = 0x02f7e45f,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x100b3215,
+       .temp_alert_config              = 0x08000a05,
+       .emif_ddr_phy_ctlr_1_init       = 0x0E30400d,
+       .emif_ddr_phy_ctlr_1            = 0x0E30400d,
+       .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
+       .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
+       .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
+       .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
+       .emif_ddr_ext_phy_ctrl_5        = 0xC330CC33,
+};
+
 const struct emif_regs emif_regs_266_mhz_2cs = {
        .sdram_config_init              = 0x80800EBA,
        .sdram_config                   = 0x808022BA,
@@ -109,6 +128,29 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
        .emif_rd_wr_exec_thresh         = 0x00000305
 };
 
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
+       .sdram_config_init              = 0x61851B32,
+       .sdram_config                   = 0x61851B32,
+       .ref_ctrl                       = 0x00001035,
+       .sdram_tim1                     = 0xCCCF36B3,
+       .sdram_tim2                     = 0x308F7FDA,
+       .sdram_tim3                     = 0x027F88A8,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x1007190B,
+       .temp_alert_config              = 0x00000000,
+       .emif_ddr_phy_ctlr_1_init       = 0x0030400A,
+       .emif_ddr_phy_ctlr_1            = 0x0034400A,
+       .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
+       .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
+       .emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
+       .emif_rd_wr_lvl_rmp_win         = 0x00000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_ctl             = 0x00000000,
+       .emif_rd_wr_exec_thresh         = 0x40000305
+};
+
 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
        .dmm_lisa_map_0 = 0x0,
        .dmm_lisa_map_1 = 0x0,
@@ -125,8 +167,12 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
        case OMAP5432_ES1_0:
                *regs = &emif_regs_ddr3_532_mhz_1cs;
                break;
+       case OMAP5430_ES2_0:
+               *regs = &emif_regs_532_mhz_2cs_es2;
+               break;
+       case OMAP5432_ES2_0:
        default:
-               *regs = &emif_regs_ddr3_532_mhz_1cs;
+               *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
        }
 }
 
@@ -210,6 +256,28 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
        0x00000057
 };
 
+const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+       0x50D4350D,
+       0x00000D43,
+       0x04010040,
+       0x01004010,
+       0x00001004,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x80080080,
+       0x00800800,
+       0x08102040,
+       0x00000002,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000057
+};
+
 const struct lpddr2_mr_regs mr_regs = {
        .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
        .mr2    = 0x6,
@@ -222,13 +290,16 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
 {
        switch (omap_revision()) {
        case OMAP5430_ES1_0:
+       case OMAP5430_ES2_0:
                *regs = ext_phy_ctrl_const_base;
                break;
        case OMAP5432_ES1_0:
                *regs = ddr3_ext_phy_ctrl_const_base_es1;
                break;
+       case OMAP5432_ES2_0:
        default:
-               *regs = ddr3_ext_phy_ctrl_const_base_es1;
+               *regs = ddr3_ext_phy_ctrl_const_base_es2;
+
        }
 }
 

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 71935d857972684752c3b987c021c655cb482990..ba2775b0a3bb73ee53c121661694e031005fd90f 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -168,6 +168,12 @@ struct s32ktimer {
 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE                         0xBC6318DC
 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE                         0x0
 
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
+
 #define EFUSE_1 0x45145100
 #define EFUSE_2 0x45145100
 #define EFUSE_3 0x45145100

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index fd530bb26a089cafd14f2cdfb02df6461e72c533..9d72fe34fc71bc3ccf97176e5aac16450f553053 100644 (file)
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -519,6 +519,7 @@
 
 #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES     0x0000C1A7
 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES      0x000001A7
+#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7
 
 /* DMM */
 #define DMM_BASE                       0x4E000040