/* setup basic address decode */
PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
li t1, 0x0
- li t2, -CONFIG_SYS_MEM_SIZE
+ li t2, -CONFIG_SYS_SDRAM_SIZE
sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
/* setup PCI_BAR0 memory window */
- li t1, -CONFIG_SYS_MEM_SIZE
+ li t1, -CONFIG_SYS_SDRAM_SIZE
sw t1, MSC01_PCI_BAR0_OFS(t0)
/* setup PCI to SysCon/CPU translation */
#else
# define CONFIG_SYS_SDRAM_BASE 0x80000000
#endif
-#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000