armv8: K3: j721e: Add DSP internal memory regions in MMU table

The A72 U-Boot code supports early load and boot of a number of
remote processors including the C66_0 and C66_1 DSPs. The current
code supports only loading into the DDR regions which were already
given the appropriate memory attributes. The C66 DSPs also have L1
and L2 internal memory regions that can behave as normal-memories.

Add a new entry to the J721E MMU table covering these regions with
the appropriate memory attributes to allow the A72 U-Boot code to
support loading directly into these memory regions.

Signed-off-by: Suman Anna <s-anna@ti.com>

diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index b1d1d6e494fce076d84093ad851a17d7303ccabf..95f830b7ffe43304b36e05d97cfa07311f155667 100644 (file)
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -67,7 +67,7 @@ struct mm_region *mem_map = am654_mem_map;
 
 #ifdef CONFIG_SOC_K3_J721E
 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
-#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
 
 /* ToDo: Add 64bit IO */
 struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
@@ -109,6 +109,12 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
                         PTE_BLOCK_NON_SHARE |
                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               .virt = 0x4d80000000UL,
+               .phys = 0x4d80000000UL,
+               .size = 0x0002000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+                        PTE_BLOCK_INNER_SHARE
        }, {
                /* List terminator */
                0,