clk: starfive: jh7110: Add watchdog clocks

Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110
watchdog device.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index a835541e48e960bfaba11b0d573fe14b9a479de6..a38694809a0068fbf55191ed872f5bb7bd81e995 100644 (file)
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -434,6 +434,15 @@ static int jh7110_syscrg_init(struct udevice *dev)
               starfive_clk_gate(priv->reg,
                                 "i2c5_apb", "apb0",
                                 OFFSET(JH7110_SYSCLK_I2C5_APB)));
+       /* Watchdog clocks */
+       clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB),
+              starfive_clk_gate(priv->reg,
+                                "wdt_apb", "apb0",
+                                OFFSET(JH7110_SYSCLK_WDT_APB)));
+       clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE),
+              starfive_clk_gate(priv->reg,
+                                "wdt_core", "oscillator",
+                                OFFSET(JH7110_SYSCLK_WDT_CORE)));
 
        /* enable noc_bus_stg_axi clock */
        if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))