ARM: vf610: Enable external 32KHz oscillator

Enable the SCSC (Slow Clock Source Controller) and select the external
32KHz oscillator. This improves the accuracy of the RTC.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>

diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 724682c683c70d1f94b0d6c43e005bd63215a12a..78708e22ac32037b56c4e52dae357c413810a5de 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -199,6 +199,7 @@ struct anadig_reg {
 #define CCM_CCGR2_PORTD_CTRL_MASK              (0x3 << 24)
 #define CCM_CCGR2_PORTE_CTRL_MASK              (0x3 << 26)
 #define CCM_CCGR3_ANADIG_CTRL_MASK             0x3
+#define CCM_CCGR3_SCSC_CTRL_MASK        (0x3 << 4)
 #define CCM_CCGR4_WKUP_CTRL_MASK               (0x3 << 20)
 #define CCM_CCGR4_CCM_CTRL_MASK                        (0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK                        (0x3 << 24)

diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 866b30372d20c162fd3dd0f9060a91de64df625d..aa60031b785a7d979f58e5d3f46ccdaa6ca7ef7b 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -65,7 +65,7 @@
 #define QSPI0_BASE_ADDR                (AIPS0_BASE_ADDR + 0x00044000)
 #define IOMUXC_BASE_ADDR       (AIPS0_BASE_ADDR + 0x00048000)
 #define ANADIG_BASE_ADDR       (AIPS0_BASE_ADDR + 0x00050000)
-#define SCSCM_BASE_ADDR                (AIPS0_BASE_ADDR + 0x00052000)
+#define SCSC_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00052000)
 #define ASRC_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00060000)
 #define SPDIF_BASE_ADDR                (AIPS0_BASE_ADDR + 0x00061000)
 #define ESAI_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00062000)
@@ -264,6 +264,9 @@
 #define SRC_SRSR_WDOG_A5                               (0x1 << 3)
 #define SRC_SRSR_POR_RST                               (0x1 << 0)
 
+/* Slow Clock Source Controller Module (SCSC) */
+#define SCSC_SOSC_CTR_SOSC_EN            0x1
+
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 
@@ -448,6 +451,12 @@ struct mscm_ir {
        u16 rsvd3[848];
 };
 
+/* SCSC */
+struct scsc_reg {
+       u32 sirc_ctr;
+       u32 sosc_ctr;
+};
+
 #endif /* __ASSEMBLER__*/
 
 #endif /* __ASM_ARCH_IMX_REGS_H__ */

diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index eb275423754e5d039c8bfa9850d517a0e142b366..4160acdcc99cb5942466fa45f73b1bd8aa756059 100644 (file)
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -227,7 +227,7 @@ static void clock_init(void)
                CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
                CCM_CCGR2_QSPI0_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
-               CCM_CCGR3_ANADIG_CTRL_MASK);
+               CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
                CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
                CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
@@ -308,9 +308,20 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+       struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
+
        /* address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+       /*
+        * Enable external 32K Oscillator
+        *
+        * The internal clock experiences significant drift
+        * so we must use the external oscillator in order
+        * to maintain correct time in the hwclock
+        */
+       setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
+
        return 0;
 }