mpc83xx: Get rid of CONFIG_SYS_DDR_BASE

CONFIG_SYS_DDR_BASE is specific to mpc83xx an is always set to the same
value as CONFIG_SYS_SDRAM_BASE. Just use CONFIG_SYS_SDRAM_BASE instead.

Signed-off-by: Mario Six <mario.six@gdsys.cc>

diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
index a46d0b6da6371b6367ab3b02cf40ea193774bfa2..4c220fa8e1353cc485e1f5a48c03d24db17b2647 100644 (file)
--- a/board/esd/vme8349/vme8349.c
+++ b/board/esd/vme8349/vme8349.c
@@ -38,7 +38,7 @@ int dram_init(void)
                return -ENXIO;
 
        /* DDR SDRAM - Main memory */
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
 
        msize = spd_sdram();
 

diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index 772688186b50bbe2a0da0e776db0b3771592dc3e..2dc6d7f5f5f453a7d48bbd84912c91d12125609f 100644 (file)
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -79,7 +79,7 @@ int dram_init(void)
                return -ENXIO;
 
        /* DDR SDRAM - Main SODIMM */
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
 
        msize = fixed_sdram();
 

diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
index 869538feb922681b37a7e0b11985f4a5dea6eccf..61b95c601e67defb879a17ca80c0dc2d67302818 100644 (file)
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ b/board/freescale/mpc832xemds/mpc832xemds.c
@@ -98,7 +98,7 @@ int dram_init(void)
                return -ENXIO;
 
        /* DDR SDRAM - Main SODIMM */
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
 
        msize = fixed_sdram();
 

diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index d40ed3742e02f251c24d18dec93b802d16f072d9..ea018e5d2013afe5c0a44f145b6d29d7e3733edd 100644 (file)
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -56,7 +56,7 @@ int dram_init(void)
                return -ENXIO;
 
        /* DDR SDRAM - Main SODIMM */
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
 #if defined(CONFIG_SPD_EEPROM)
 #ifndef CONFIG_SYS_FSL_DDR2
        msize = spd_sdram() * 1024 * 1024;

diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 62bcf23571127a993801565788932fcf60c1044f..aaaea7ce89f84545090484d55cfdd12ec651fc75 100644 (file)
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -132,7 +132,7 @@ int dram_init(void)
                return -ENXIO;
 
        /* DDR SDRAM - Main SODIMM */
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
 #ifdef CONFIG_SPD_EEPROM
        msize = spd_sdram();
 #else

diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
index d547af4b05acfc28438aacb8ff82f33cd79e99f0..a37ca8a2f4417543ebcaf27c9b2b40b252b10aa9 100644 (file)
--- a/board/ids/ids8313/ids8313.c
+++ b/board/ids/ids8313/ids8313.c
@@ -96,7 +96,7 @@ int fixed_sdram(unsigned long config)
        setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
        /* now check the real size */
        disable_addr_trans();
-       msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+       msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
        enable_addr_trans();
 #endif
        return msize;

diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 1fd6f919014641206e03a101057c43eceb8c5842..880ce67fa6ca0de8219f63a7e2bf9a845a431427 100644 (file)
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -311,7 +311,7 @@ static int fixed_sdram(void)
 
        msize = CONFIG_SYS_DDR_SIZE << 20;
        disable_addr_trans();
-       msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+       msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
        enable_addr_trans();
        msize /= (1024 * 1024);
        if (CONFIG_SYS_DDR_SIZE != msize) {
@@ -338,7 +338,7 @@ int dram_init(void)
                return -ENXIO;
 
        out_be32(&im->sysconf.ddrlaw[0].bar,
-               CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
+               CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
        msize = fixed_sdram();
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)

diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index b8ba29ac6da213b44c1aeab65b2321132f390faf..5584b3d17960770200bce33bf2f428e9f5c8a43b 100644 (file)
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -45,7 +45,7 @@ int dram_init(void)
                return -1;
 
        /* DDR SDRAM - Main SODIMM */
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
 #if defined(CONFIG_SPD_EEPROM)
        msize = spd_sdram();
 #else

diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index c75251e132c91d5d68154cde347e79883b761b75..04941b26be457ceb08ae19827e15c000a9eb686d 100644 (file)
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -72,13 +72,13 @@ int dram_init(void)
        int cs;
 
        /* during size detection, set up the max DDRLAW size */
-       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE;
        im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
 
        /* set CS bounds to maximum size */
        for(cs = 0; cs < 4; ++cs) {
                set_cs_bounds(cs,
-                       CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
+                       CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS),
                        DDR_MAX_SIZE_PER_CS);
 
                set_cs_config(cs, INITIAL_CS_CONFIG);
@@ -102,7 +102,7 @@ int dram_init(void)
                debug("\nDetecting Bank%d\n", cs);
 
                bank_size = get_ddr_bank_size(cs,
-                       (long *)(CONFIG_SYS_DDR_BASE + size));
+                       (long *)(CONFIG_SYS_SDRAM_BASE + size));
                size += bank_size;
 
                debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);

diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index f0fc1fe3b31d8097661e9ef29a02bfa21d0627ac..609585bc653a749f18343773fb8a798be0fd9813 100644 (file)
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -80,7 +80,7 @@ static long fixed_sdram(void)
 
        /* now check the real size */
        disable_addr_trans ();
-       msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
+       msize = get_ram_size (CONFIG_SYS_SDRAM_BASE, msize);
        enable_addr_trans ();
 #endif
 

diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index e625f8709cb1c14d27d5160d08641bef0b6aa5d2..d9361fd8a03370d55e4fef67e13d5a83858759e2 100644 (file)
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -36,9 +36,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
index 08c5b56da71daa04650e9cd745f42b3880d505c2..08c83996c732253e7f68548382bb1f846b518704 100644 (file)
--- a/include/configs/MPC8313ERDB_NAND.h
+++ b/include/configs/MPC8313ERDB_NAND.h
@@ -86,9 +86,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not

diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
index 2a39ffa6c2c2ff9bfbe8a22b1e99e51c7546d34a..169cc09d06b17e17d01162b05ab1a1289778338c 100644 (file)
--- a/include/configs/MPC8313ERDB_NOR.h
+++ b/include/configs/MPC8313ERDB_NOR.h
@@ -58,9 +58,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index b49022b916d1977bc40a9d441d90e119532a1c72..c5a229deb4cd13b7b4e92b4d1f3325dbcd77c57a 100644 (file)
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -34,9 +34,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 497c60bcdaa798c64fa16369515e09faefc503f6..3e6febfc9d35b88a4ced7682ce0703f7389d0078 100644 (file)
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -23,9 +23,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE    0x00000000      /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 #undef CONFIG_SPD_EEPROM
 #if defined(CONFIG_SPD_EEPROM)

diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 520f01f177dc5fdbbaaf3aa97399681f5a91d2e8..4b3f70c916cb34e7f273bf521e7cd0528b8cd6fa 100644 (file)
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -20,9 +20,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE    0x00000000      /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDRCDR      0x73000002      /* DDR II voltage is 1.8V */
 
 #undef CONFIG_SPD_EEPROM

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 2043344524848f191eb01eaf43ff7e72a02cfec9..1a96be0895c130c7d6fa36ae301c33243daa7010 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -52,9 +52,8 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CONFIG_SYS_DDR_BASE    0x00000000      /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING

diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index 70fc29e8ade5a406659696d5057effc04d975734..311f87b5b3c13873f1070787e41dfc1a4408affc 100644 (file)
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -52,9 +52,8 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CONFIG_SYS_DDR_BASE    0x00000000      /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 6f040a3d6dc791c21a1f6d8afdace5d494d75d2c..bb3bcfcc44800625ea0fd9127065b639dc92e30c 100644 (file)
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -142,9 +142,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_SYS_MEMTEST_START       0x1000  /* memtest region */
 #define CONFIG_SYS_MEMTEST_END         0x2000

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 5f0050a97d5bf3bb0e77a876889326bf309949e5..e34a36cadd884b37b64dc71ef7fc597b51a234a7 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -35,9 +35,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_SYS_DDRCDR_VALUE                (DDRCDR_DHC_EN \

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index ef23d0040859e6470f3748da55bcbce4d5c94368..33d4ced92f79a633e19f836d8ba39df76961fd1e 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -58,9 +58,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  0x03000000
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 8171f8531ba1ad5d4a992ef418516def2725bd3c..53fac4d675a8b129671d5b6ba072bc02b973d090 100644 (file)
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -24,9 +24,8 @@
  * DDR Setup
  */
                                /* DDR is system memory*/
-#define CONFIG_SYS_DDR_BASE    0x00000000
-#define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE  0x00000000
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define DDR_CASLAT_25          /* CASLAT set to 2.5 */
 #undef CONFIG_DDR_ECC          /* only for ECC DDR module */
 #undef CONFIG_SPD_EEPROM       /* do not use SPD EEPROM for DDR setup */

diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
index a0642aef1124b30e612acf61a1bfe2ce0f524ef1..f14e5faafa658a24ae58a5bce96db9c43b9ab66a 100644 (file)
--- a/include/configs/caddy2.h
+++ b/include/configs/caddy2.h
@@ -51,9 +51,8 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CONFIG_SYS_DDR_BASE            0x00000000      /* DDR is sys memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000      /* DDR is sys memory*/
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING

diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 0919bb544d0a45665ac6b09176e0d3580e5aac45..ae3fcfd3d79a4ad90bf0c40de0e3477dc2e88632 100644 (file)
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -24,9 +24,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 174c181ffafacecbb240974e129ade5b6591d9f8..504a136daab23566098d8341b758f92ce2fcad21 100644 (file)
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -51,9 +51,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters,

diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index 7034c7033f27593d4025cc3929326b0df299126d..5c4df18ca64d2b4a8ca887666d2f5b9c82120970 100644 (file)
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h
@@ -43,11 +43,10 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index bbf3783ef93859d4b94f0d56083dbbdfa8fb48c0..2e8affb618014dc63812d7234873cf7c5cda1099 100644 (file)
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -28,11 +28,10 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h
index 77dc6a93b1946443f723e45fc9b98203f6205941..3be53285dbcfd4def19fbc74278fefb984e5602b 100644 (file)
--- a/include/configs/kmopti2.h
+++ b/include/configs/kmopti2.h
@@ -48,11 +48,10 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
index 561ae7a14839753534ca895640a33f580c02b6bc..74e719cc79ff59feceb1603c6644b820e67ae83b 100644 (file)
--- a/include/configs/kmsupx5.h
+++ b/include/configs/kmsupx5.h
@@ -48,11 +48,10 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
index b4ebde8ba5a5be1bdc3533784e0fd88a2af55c6d..c6913838ce79c0062224ef10866fba6cc1b4c747 100644 (file)
--- a/include/configs/kmtegr1.h
+++ b/include/configs/kmtegr1.h
@@ -55,11 +55,10 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h
index 80f6f4daa46ab70f608ea89b8c2169be4298adcc..4af86195c5e5e9e585978f6a5f96846bd9e47bfe 100644 (file)
--- a/include/configs/kmtepr2.h
+++ b/include/configs/kmtepr2.h
@@ -48,11 +48,10 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h
index 9e301a9728db9dca003a42f6c79c099ad0b1f8f5..d8f4d269ed401a32cdb429d7f7615b42d6599f71 100644 (file)
--- a/include/configs/kmvect1.h
+++ b/include/configs/kmvect1.h
@@ -47,11 +47,10 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index aca4a655e03d381cc93af87f95c0cc9d36dec88c..8836b70b762770a53f961847ca601c246a589a66 100644 (file)
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -39,9 +39,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 6bad65113393a97ac7df7e410a3e48a8edc4b4d5..709387ecf7996e19309e73ba55e4b92ef975ef70 100644 (file)
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -46,9 +46,8 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING

diff --git a/include/configs/strider.h b/include/configs/strider.h
index 69e22fb141efcb279d559a5014194cd36731c914..c01531c3ca235132c5dec47bc5b7bdd36d586c57 100644 (file)
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -24,9 +24,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \

diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index ad3323fd0e107e9d01f5f3c75d8a0fa661df6294..3521de8d2ee582157f5f2e6869c84b37df597395 100644 (file)
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -45,11 +45,10 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE  0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h
index 466f75a44eb90a890dc58dd4e34e7b2f9beb8bad..86e402ae233c4690c0407b09449c39a99f6967fe 100644 (file)
--- a/include/configs/tuge1.h
+++ b/include/configs/tuge1.h
@@ -48,11 +48,10 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
index 02e24f002a8270192e36284c0c116f4882a41d0f..ec1ac399a0c09a6f456f7edcaf809094984a2c94 100644 (file)
--- a/include/configs/tuxx1.h
+++ b/include/configs/tuxx1.h
@@ -48,11 +48,10 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 8b20bfd10033240707b0a87736340714621681c6..cd6c686b890e30fdff77de2ace6a519b71d88330 100644 (file)
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -34,9 +34,8 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not

diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index d50a5263a708a0811623974b72b5aba898efd470..14a84fabc97e86f000512be5bc3da9e5189a073a 100644 (file)
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -51,9 +51,8 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CONFIG_SYS_DDR_BASE            0x00000000      /* DDR is sys memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000      /* DDR is sys memory*/
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING

diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index c6c4689a2f13a9e1da57300a2d5c6f613594b760..992bcc3d8fd1ef021c3283f875a5bf229dc488f0 100644 (file)
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2254,7 +2254,6 @@ CONFIG_SYS_DDRCDR_VALUE
 CONFIG_SYS_DDRD
 CONFIG_SYS_DDRTC
 CONFIG_SYS_DDRUA
-CONFIG_SYS_DDR_BASE
 CONFIG_SYS_DDR_BLOCK1_SIZE
 CONFIG_SYS_DDR_BLOCK2_BASE
 CONFIG_SYS_DDR_CDR_1