crypto/fsl: Make CAAM transactions cacheable

This commit solves CAAM coherency issue on ls2080. When caches are
enabled and CAAM's DMA's AXI transcations are not made cacheable,
Core reads/writes data from/to caches and CAAM does from main memory.
This forces data flushes to synchronize various data structures. But
even if any data in proximity of these structures is read by core,
these structures again are fetched in caches.

To avoid this problem, either all the data that CAAM accesses can be
made cache line aligned or CAAM transcations can be made cacheable.

So, this commit makes CAAM transcations as write back with write and
read allocate.

Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 93c24712d1ef824396841a6913d75c2fe0c61feb..3fc418a8c42b142645cbffa29c470a6de868102e 100644 (file)
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -543,7 +543,20 @@ int sec_init(void)
        uint32_t liodn_s;
 #endif
 
+       /*
+        * Modifying CAAM Read/Write Attributes
+        * For LS2080A and LS2085A
+        * For AXI Write - Cacheable, Write Back, Write allocate
+        * For AXI Read - Cacheable, Read allocate
+        * Only For LS2080a and LS2085a, to solve CAAM coherency issues
+        */
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+       mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
+       mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
+#else
        mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
+#endif
+
 #ifdef CONFIG_PHYS_64BIT
        mcr |= (1 << MCFGR_PS_SHIFT);
 #endif

diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 545d964cedd5b8c2a7969a29a00df12f577a41b0..1642dbbf4c22c9c878261bf8f342de648f1ef111 100644 (file)
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -23,6 +23,9 @@
 #define MCFGR_PS_SHIFT          16
 #define MCFGR_AWCACHE_SHIFT    8
 #define MCFGR_AWCACHE_MASK     (0xf << MCFGR_AWCACHE_SHIFT)
+#define MCFGR_ARCACHE_SHIFT    12
+#define MCFGR_ARCACHE_MASK     (0xf << MCFGR_ARCACHE_SHIFT)
+
 #define JR_INTMASK       0x00000001
 #define JRCR_RESET                  0x01
 #define JRINT_ERR_HALT_INPROGRESS   0x4