sunxi: Cache line size definition

Sunxi platforms use ARM Cortex A8, A7 and A15 (unsupported yet) CPU cores,
which all have 64 bytes cache line size.

This is required to e.g. enable USB gadget.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index f80f006e3db6fc13b3a716c39266b9b4df519554..d829899c07db59dd8605bf473496856d1d68f101 100644 (file)
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -66,6 +66,9 @@
 # define CONFIG_SYS_NS16550_COM5               SUNXI_R_UART_BASE
 #endif
 
+/* CPU */
+#define CONFIG_SYS_CACHELINE_SIZE      64
+
 /* DRAM Base */
 #define CONFIG_SYS_SDRAM_BASE          0x40000000
 #define CONFIG_SYS_INIT_RAM_ADDR       0x0