CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=57
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_AM35X=y
CONFIG_BCH=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
+CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=4
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
+CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=147
CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
+CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=4
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_HAS_OMAP_EHCI_PHY1_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY1_RESET_GPIO=1
+CONFIG_HAS_OMAP_EHCI_PHY2_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY2_RESET_GPIO=62
CONFIG_USB_OMAP3=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_HAS_OMAP_EHCI_PHY2_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY2_RESET_GPIO=80
+CONFIG_HAS_OMAP_EHCI_PHY3_RESET_GPIO=y
+CONFIG_OMAP_EHCI_PHY3_RESET_GPIO=79
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
Enables support for the on-chip EHCI controller on OMAP3 and later
SoCs.
+if USB_EHCI_OMAP
+
+config HAS_OMAP_EHCI_PHY1_RESET_GPIO
+ bool "PHY #1 requires a GPIO hold to it in RESET while PHY settles"
+ help
+ Enable this to be able to configure the GPIO number used to hold the
+ PHY in RESET for enough time until the PHY is settled and ready.
+
+config OMAP_EHCI_PHY1_RESET_GPIO
+ int "GPIO number to hold PHY #1 in RESET"
+ depends on HAS_OMAP_EHCI_PHY1_RESET_GPIO
+
+config HAS_OMAP_EHCI_PHY2_RESET_GPIO
+ bool "PHY #2 requires a GPIO hold to it in RESET while PHY settles"
+ help
+ Enable this to be able to configure the GPIO number used to hold the
+ PHY in RESET for enough time until the PHY is settled and ready.
+
+config OMAP_EHCI_PHY2_RESET_GPIO
+ int "GPIO number to hold PHY #2 in RESET"
+ depends on HAS_OMAP_EHCI_PHY2_RESET_GPIO
+
+config HAS_OMAP_EHCI_PHY3_RESET_GPIO
+ bool "PHY #3 requires a GPIO hold to it in RESET while PHY settles"
+ help
+ Enable this to be able to configure the GPIO number used to hold the
+ PHY in RESET for enough time until the PHY is settled and ready.
+
+config OMAP_EHCI_PHY3_RESET_GPIO
+ int "GPIO number to hold PHY #3 in RESET"
+ depends on HAS_OMAP_EHCI_PHY3_RESET_GPIO
+
+endif
+
config USB_EHCI_VF
bool "Support for Vybrid on-chip EHCI USB controller"
depends on ARCH_VF610
*/
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_USB_EHCI_OMAP
-#else
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
#endif
/* I2C */
#endif /* CONFIG_SPL_OS_BOOT */
#endif /* CONFIG_MTD_RAW_NAND */
-/* USB EHCI */
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
-
/* Enable Multi Bus support for I2C */
#define CONFIG_I2C_MULTI_BUS
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_USB_EHCI_OMAP
#endif
-#ifdef CONFIG_USB_EHCI_OMAP
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 4
-#endif
/* Board NAND Info. */
#ifdef CONFIG_MTD_RAW_NAND
*/
/* USB UHH support options */
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
-#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
/* USB Networking options */
/* USB UHH support options */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
-#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
-
/* Enabled commands */
/* USB Networking options */
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
-/* EHCI */
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07