fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0

Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0.
This decreases data burst rate with which data packets are posted from the TX
latency FIFO to compensate for latencies in DDR pipeline during DMA.
This avoids Tx buffer underruns and leads to successful usb writes

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 1d012db92e6ff2cb2618321c550e70f6aa9f7177..6cb4d986685c037757aca191dc9490e2a38c3a07 100644 (file)
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -18,6 +18,8 @@
 
 #include "ehci.h"
 
+static void set_txfifothresh(struct usb_ehci *, u32);
+
 /* Check USB PHY clock valid */
 static int usb_phy_clk_valid(struct usb_ehci *ehci)
 {
@@ -123,6 +125,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
        in_le32(&ehci->usbmode);
 
+       if (SVR_SOC_VER(get_svr()) == SVR_T4240 &&
+           IS_SVR_REV(get_svr(), 2, 0))
+               set_txfifothresh(ehci, TXFIFOTHRESH);
+
        return 0;
 }
 
@@ -134,3 +140,17 @@ int ehci_hcd_stop(int index)
 {
        return 0;
 }
+
+/*
+ * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
+ * to counter DDR latencies in writing data into Tx buffer.
+ * This prevents Tx buffer from getting underrun
+ */
+static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
+{
+       u32 cmd;
+       cmd = ehci_readl(&ehci->txfilltuning);
+       cmd &= ~TXFIFO_THRESH_MASK;
+       cmd |= TXFIFO_THRESH(txfifo_thresh);
+       ehci_writel(&ehci->txfilltuning, cmd);
+}

diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 734305b9dba25fd1e1809e96db81781da0ea1659..c9ee1d5bf6264b257f6042b348c20fa2f6de7606 100644 (file)
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -163,6 +163,13 @@
 #define CONFIG_SYS_FSL_USB2_ADDR       0
 #endif
 
+/*
+ * Increasing TX FIFO threshold value from 2 to 4 decreases
+ * data burst rate with which data packets are posted from the TX
+ * latency FIFO to compensate for latencies in DDR pipeline during DMA
+ */
+#define TXFIFOTHRESH           4
+
 /*
  * USB Registers
  */