/* Do any chip-specific cache config */
void config_cache(void);
-#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
-/* Do chip-specific vpr config */
-void config_vpr(void);
-#else
-static inline void config_vpr(void)
-{
-}
-#endif
-
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
bool tegra_cpu_is_non_secure(void);
#endif
--- /dev/null
+/*
+ * (C) Copyright 2015
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_TEGRA_GPU_H
+#define __ASM_ARCH_TEGRA_GPU_H
+
+#if defined(CONFIG_TEGRA_GPU)
+
+void config_gpu(void);
+bool gpu_configured(void);
+
+#else /* CONFIG_TEGRA_GPU */
+
+static inline void config_gpu(void)
+{
+}
+
+static inline bool gpu_configured(void)
+{
+ return false;
+}
+
+#endif /* CONFIG_TEGRA_GPU */
obj-y += powergate.o
obj-y += xusb-padctl.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
-#TCW Fix this to use a common config switch (CONFIG_LOCK_VPR?)
-obj-$(CONFIG_TEGRA124) += vpr.o
-obj-$(CONFIG_TEGRA210) += vpr.o
+obj-$(CONFIG_TEGRA_GPU) += gpu.o
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
ifndef CONFIG_SPL_BUILD
/* enable SMMU */
smmu_enable();
-
- /* init vpr */
- config_vpr();
}
#endif
#include <asm/arch-tegra/sys_proto.h>
#include <asm/arch-tegra/uart.h>
#include <asm/arch-tegra/warmboot.h>
+#include <asm/arch-tegra/gpu.h>
#ifdef CONFIG_TEGRA_CLOCK_SCALING
#include <asm/arch/emc.h>
#endif
clock_init();
clock_verify();
+ config_gpu();
+
#ifdef CONFIG_TEGRA_SPI
pin_mux_spi();
#endif
/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
#include <asm/arch/tegra.h>
#include <asm/arch/mc.h>
-/* Configures VPR. Right now, all we do is turn it off. */
-void config_vpr(void)
+#include <fdt_support.h>
+
+static bool _configured;
+
+void config_gpu(void)
{
struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
&mc->mc_video_protect_reg_ctrl);
/* read back to ensure the write went through */
readl(&mc->mc_video_protect_reg_ctrl);
+
+ debug("configured VPR\n");
+
+ _configured = true;
+}
+
+bool vpr_configured(void)
+{
+ return _configured;
}
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+/* GPU needs setup */
+#define CONFIG_TEGRA_GPU
+
#endif /* _TEGRA124_COMMON_H_ */
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+/* GPU needs setup */
+#define CONFIG_TEGRA_GPU
+
#endif /* _TEGRA210_COMMON_H_ */