ARM: dts: imx: Rename imx8mp-dhcom{-pdk2,}-boot.dtsi

Rename imx8mp-dhcom-pdk2-u-boot.dtsi to imx8mp-dhcom-u-boot.dtsi, since
this file is shared by PDK2, PicoITX and DRC02. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi
index ae838caebcf7b999aeade1dce55efa380a1c81f8..be2d4fb184a5a02e5fcdbf2f242bb3f7d9037b58 100644 (file)
--- a/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi
@@ -3,139 +3,4 @@
  * Copyright (C) 2022 Marek Vasut <marex@denx.de>
  */
 
-#include "imx8mp-u-boot.dtsi"
-
-/ {
-       aliases {
-               eeprom0 = &eeprom0;
-               eeprom1 = &eeprom1;
-               mmc0 = &usdhc2; /* MicroSD */
-               mmc1 = &usdhc3; /* eMMC */
-               mmc2 = &usdhc1; /* SDIO */
-       };
-
-       config {
-               dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>;
-       };
-
-       wdt-reboot {
-               compatible = "wdt-reboot";
-               wdt = <&wdog1>;
-               u-boot,dm-spl;
-       };
-};
-
-&buck4 {
-       u-boot,dm-spl;
-};
-
-&buck5 {
-       u-boot,dm-spl;
-};
-
-&eqos {
-       /delete-property/ assigned-clocks;
-       /delete-property/ assigned-clock-parents;
-       /delete-property/ assigned-clock-rates;
-};
-
-&gpio1 {
-       u-boot,dm-spl;
-};
-
-&gpio2 {
-       u-boot,dm-spl;
-};
-
-&gpio3 {
-       u-boot,dm-spl;
-};
-
-&gpio4 {
-       u-boot,dm-spl;
-};
-
-&gpio5 {
-       u-boot,dm-spl;
-};
-
-&i2c3 {
-       u-boot,dm-spl;
-};
-
-&pinctrl_i2c3 {
-       u-boot,dm-spl;
-};
-
-&pinctrl_i2c3_gpio {
-       u-boot,dm-spl;
-};
-
-&pinctrl_pmic {
-       u-boot,dm-spl;
-};
-
-&pinctrl_uart1 {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2 {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2_100mhz {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2_200mhz {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc2_vmmc {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3 {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3_100mhz {
-       u-boot,dm-spl;
-};
-
-&pinctrl_usdhc3_100mhz {
-       u-boot,dm-spl;
-};
-
-&pmic {
-       u-boot,dm-spl;
-
-       regulators {
-               u-boot,dm-spl;
-       };
-};
-
-&reg_usdhc2_vmmc {
-       u-boot,dm-spl;
-};
-
-&uart1 {
-       u-boot,dm-spl;
-};
-
-/* SDIO WiFi */
-&usdhc1 {
-       status = "disabled";
-};
-
-&usdhc2 {
-       u-boot,dm-spl;
-};
-
-&usdhc3 {
-       u-boot,dm-spl;
-};
-
-&wdog1 {
-       u-boot,dm-spl;
-};
+#include "imx8mp-dhcom-u-boot.dtsi"

diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
new file mode 100644 (file)
index 0000000..ae838ca
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+       aliases {
+               eeprom0 = &eeprom0;
+               eeprom1 = &eeprom1;
+               mmc0 = &usdhc2; /* MicroSD */
+               mmc1 = &usdhc3; /* eMMC */
+               mmc2 = &usdhc1; /* SDIO */
+       };
+
+       config {
+               dh,ram-coding-gpios = <&gpio3 22 0>, <&gpio3 23 0>, <&gpio3 24 0>;
+       };
+
+       wdt-reboot {
+               compatible = "wdt-reboot";
+               wdt = <&wdog1>;
+               u-boot,dm-spl;
+       };
+};
+
+&buck4 {
+       u-boot,dm-spl;
+};
+
+&buck5 {
+       u-boot,dm-spl;
+};
+
+&eqos {
+       /delete-property/ assigned-clocks;
+       /delete-property/ assigned-clock-parents;
+       /delete-property/ assigned-clock-rates;
+};
+
+&gpio1 {
+       u-boot,dm-spl;
+};
+
+&gpio2 {
+       u-boot,dm-spl;
+};
+
+&gpio3 {
+       u-boot,dm-spl;
+};
+
+&gpio4 {
+       u-boot,dm-spl;
+};
+
+&gpio5 {
+       u-boot,dm-spl;
+};
+
+&i2c3 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_i2c3 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_i2c3_gpio {
+       u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+       u-boot,dm-spl;
+};
+
+&pinctrl_uart1 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_100mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_200mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_vmmc {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_100mhz {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_100mhz {
+       u-boot,dm-spl;
+};
+
+&pmic {
+       u-boot,dm-spl;
+
+       regulators {
+               u-boot,dm-spl;
+       };
+};
+
+&reg_usdhc2_vmmc {
+       u-boot,dm-spl;
+};
+
+&uart1 {
+       u-boot,dm-spl;
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+       status = "disabled";
+};
+
+&usdhc2 {
+       u-boot,dm-spl;
+};
+
+&usdhc3 {
+       u-boot,dm-spl;
+};
+
+&wdog1 {
+       u-boot,dm-spl;
+};