ddr: imx8m: Return error values from LPDDR4 training

In cases when the same SPL should run on boards with i.MX8MM, that
differ in DDR configuration, it is necessary to try different
parameters and check if the training done by the firmware suceeds or
not.

Therefore we return the DDR training/initialization success to the
upper layer in order to be able to retry with different settings if
necessary.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
index 53d46256d8baf4f5afd8d3d794b61d29c5917ddd..7a2a2d8edce094b36f59b793d86997db0ef19656 100644 (file)
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -703,14 +703,14 @@ struct dram_timing_info {
 extern struct dram_timing_info dram_timing;
 
 void ddr_load_train_firmware(enum fw_type type);
-void ddr_init(struct dram_timing_info *timing_info);
-void ddr_cfg_phy(struct dram_timing_info *timing_info);
+int ddr_init(struct dram_timing_info *timing_info);
+int ddr_cfg_phy(struct dram_timing_info *timing_info);
 void load_lpddr4_phy_pie(void);
 void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
 void dram_config_save(struct dram_timing_info *info, unsigned long base);
 
 /* utils function for ddr phy training */
-void wait_ddrphy_training_complete(void);
+int wait_ddrphy_training_complete(void);
 void ddrphy_init_set_dfi_clk(unsigned int drate);
 void ddrphy_init_read_msg_block(enum fw_type type);
 

diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index 21af66e4e7f086b74a85f0b05926fcf81e5c530d..af8c1427d2edd02b3ccf5728a89247a01e5fd550 100644 (file)
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -20,9 +20,10 @@ void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
        }
 }
 
-void ddr_init(struct dram_timing_info *dram_timing)
+int ddr_init(struct dram_timing_info *dram_timing)
 {
        unsigned int tmp, initial_drate, target_freq;
+       int ret;
 
        debug("DDRINFO: start DRAM init\n");
 
@@ -98,7 +99,11 @@ void ddr_init(struct dram_timing_info *dram_timing)
         * accessing relevant PUB registers
         */
        debug("DDRINFO:ddrphy config start\n");
-       ddr_cfg_phy(dram_timing);
+
+       ret = ddr_cfg_phy(dram_timing);
+       if (ret)
+               return ret;
+
        debug("DDRINFO: ddrphy config done\n");
 
        /*
@@ -165,4 +170,6 @@ void ddr_init(struct dram_timing_info *dram_timing)
 
        /* save the dram timing config into memory */
        dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
+
+       return 0;
 }

diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/imx8m/ddrphy_train.c
index 18f7ed7fea9a3b2c622d660cf7f69551480dcd23..306af82504feec0ee310711e9a2af858236ca1ba 100644 (file)
--- a/drivers/ddr/imx/imx8m/ddrphy_train.c
+++ b/drivers/ddr/imx/imx8m/ddrphy_train.c
@@ -8,13 +8,14 @@
 #include <asm/arch/ddr.h>
 #include <asm/arch/lpddr4_define.h>
 
-void ddr_cfg_phy(struct dram_timing_info *dram_timing)
+int ddr_cfg_phy(struct dram_timing_info *dram_timing)
 {
        struct dram_cfg_param *dram_cfg;
        struct dram_fsp_msg *fsp_msg;
        unsigned int num;
        int i = 0;
        int j = 0;
+       int ret;
 
        /* initialize PHY configuration */
        dram_cfg = dram_timing->ddrphy_cfg;
@@ -60,7 +61,9 @@ void ddr_cfg_phy(struct dram_timing_info *dram_timing)
                dwc_ddrphy_apb_wr(0xd0099, 0x0);
 
                /* Wait for the training firmware to complete */
-               wait_ddrphy_training_complete();
+               ret = wait_ddrphy_training_complete();
+               if (ret)
+                       return ret;
 
                /* Halt the microcontroller. */
                dwc_ddrphy_apb_wr(0xd0099, 0x1);
@@ -83,4 +86,6 @@ void ddr_cfg_phy(struct dram_timing_info *dram_timing)
 
        /* save the ddr PHY trained CSR in memory for low power use */
        ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num);
+
+       return 0;
 }

diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c
index e60503309eb8c37d835752dbdce45a3f83396a07..863fb4389714ce34ad0ef36d9f09988012258e28 100644 (file)
--- a/drivers/ddr/imx/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c
@@ -84,7 +84,7 @@ static inline void decode_streaming_message(void)
        debug("\n");
 }
 
-void wait_ddrphy_training_complete(void)
+int wait_ddrphy_training_complete(void)
 {
        unsigned int mail;
 
@@ -95,10 +95,10 @@ void wait_ddrphy_training_complete(void)
                        decode_streaming_message();
                } else if (mail == 0x07) {
                        debug("Training PASS\n");
-                       break;
+                       return 0;
                } else if (mail == 0xff) {
-                       printf("Training FAILED\n");
-                       break;
+                       debug("Training FAILED\n");
+                       return -1;
                }
        }
 }