powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache

While enabling L2 cache, the value of L2PE (L2 cache parity/ECC
error checking enable) must not be changed while the L2 cache is
enabled.
So, L2PE must be set before enabling L2 cache.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 82a151a0d0e14726e2a0578a5a6f0028a464409e..4c5122586854dedd236e296aa0915447f2d9f940 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -720,16 +720,39 @@ enable_l2_cluster_l2:
        ori     r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
        sync
        stw     r4, 0(r3)       /* invalidate L2 */
+       /* Poll till the bits are cleared */
 1:     sync
        lwz     r0, 0(r3)
        twi     0, r0, 0
        isync
        and.    r1, r0, r4
        bne     1b
+
+       /* L2PE must be set before L2 cache is enabled */
+       lis     r4, (L2CSR0_L2PE)@h
+       ori     r4, r4, (L2CSR0_L2PE)@l
+       sync
+       stw     r4, 0(r3)       /* enable L2 parity/ECC error checking */
+       /* Poll till the bit is set */
+1:     sync
+       lwz     r0, 0(r3)
+       twi     0, r0, 0
+       isync
+       and.    r1, r0, r4
+       beq     1b
+
        lis     r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
        ori     r4, r4, (L2CSR0_L2REP_MODE)@l
        sync
        stw     r4, 0(r3)       /* enable L2 */
+       /* Poll till the bit is set */
+1:     sync
+       lwz     r0, 0(r3)
+       twi     0, r0, 0
+       isync
+       and.    r1, r0, r4
+       beq     1b
+
 delete_ccsr_l2_tlb:
        delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
 #endif