]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12
authorMarek Vasut <marek.vasut+renesas@gmail.com>
Sun, 25 Apr 2021 19:09:10 +0000 (21:09 +0200)
committerMarek Vasut <marek.vasut+renesas@gmail.com>
Fri, 21 May 2021 13:00:16 +0000 (15:00 +0200)
Synchronize R-Car Gen2 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
drivers/clk/renesas/r8a7790-cpg-mssr.c
drivers/clk/renesas/r8a7791-cpg-mssr.c
drivers/clk/renesas/r8a7792-cpg-mssr.c
drivers/clk/renesas/r8a7794-cpg-mssr.c
drivers/clk/renesas/rcar-gen2-cpg.h

index d5079da3ffbcc5cdb1fd4727840abe2543affc0f..8d616476c7188eea3494c30377df55405e3de7f3 100644 (file)
@@ -108,8 +108,8 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] = {
        DEF_MOD("tmu0",                  125,   R8A7790_CLK_CP),
        DEF_MOD("vsp1du1",               127,   R8A7790_CLK_ZS),
        DEF_MOD("vsp1du0",               128,   R8A7790_CLK_ZS),
-       DEF_MOD("vsp1-rt",               130,   R8A7790_CLK_ZS),
-       DEF_MOD("vsp1-sy",               131,   R8A7790_CLK_ZS),
+       DEF_MOD("vspr",                  130,   R8A7790_CLK_ZS),
+       DEF_MOD("vsps",                  131,   R8A7790_CLK_ZS),
        DEF_MOD("scifa2",                202,   R8A7790_CLK_MP),
        DEF_MOD("scifa1",                203,   R8A7790_CLK_MP),
        DEF_MOD("scifa0",                204,   R8A7790_CLK_MP),
index fa0e275afd6d2700a56826b265c63929ccb1d9c0..7a89613b32dcaa49942d8f3aa49cb9f235762649 100644 (file)
@@ -106,7 +106,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] = {
        DEF_MOD("tmu0",                  125,   R8A7791_CLK_CP),
        DEF_MOD("vsp1du1",               127,   R8A7791_CLK_ZS),
        DEF_MOD("vsp1du0",               128,   R8A7791_CLK_ZS),
-       DEF_MOD("vsp1-sy",               131,   R8A7791_CLK_ZS),
+       DEF_MOD("vsps",                  131,   R8A7791_CLK_ZS),
        DEF_MOD("scifa2",                202,   R8A7791_CLK_MP),
        DEF_MOD("scifa1",                203,   R8A7791_CLK_MP),
        DEF_MOD("scifa0",                204,   R8A7791_CLK_MP),
index d2225a3ff5f1fd0e432d5ddbe689101dd8282085..e18774dae4e568c56ae7c7fd15a0a36aebca77c7 100644 (file)
@@ -88,7 +88,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] = {
        DEF_MOD("tmu0",                  125,   R8A7792_CLK_CP),
        DEF_MOD("vsp1du1",               127,   R8A7792_CLK_ZS),
        DEF_MOD("vsp1du0",               128,   R8A7792_CLK_ZS),
-       DEF_MOD("vsp1-sy",               131,   R8A7792_CLK_ZS),
+       DEF_MOD("vsps",                  131,   R8A7792_CLK_ZS),
        DEF_MOD("msiof1",                208,   R8A7792_CLK_MP),
        DEF_MOD("sys-dmac1",             218,   R8A7792_CLK_ZS),
        DEF_MOD("sys-dmac0",             219,   R8A7792_CLK_ZS),
index d05f89deb14236a684712b3bccc3f49de91f2e1a..790bc1bbd924f5ab3d91828d0094f779a1cf3f3f 100644 (file)
@@ -97,7 +97,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] = {
        DEF_MOD("cmt0",                  124,   R8A7794_CLK_R),
        DEF_MOD("tmu0",                  125,   R8A7794_CLK_CP),
        DEF_MOD("vsp1du0",               128,   R8A7794_CLK_ZS),
-       DEF_MOD("vsp1-sy",               131,   R8A7794_CLK_ZS),
+       DEF_MOD("vsps",                  131,   R8A7794_CLK_ZS),
        DEF_MOD("scifa2",                202,   R8A7794_CLK_MP),
        DEF_MOD("scifa1",                203,   R8A7794_CLK_MP),
        DEF_MOD("scifa0",                204,   R8A7794_CLK_MP),
index 913c9326203822d0c885e65a957abee7973202f7..2739480dad92048b6a59e039ea8c2fac31329b19 100644 (file)
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * R-Car Gen2 Clock Pulse Generator
  *
  * Copyright (C) 2016 Cogent Embedded Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation; version 2 of the License.
  */
 
 #ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__