#include <linux/delay.h>
#include <asm/gpio.h>
-struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev)
+struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev,
- int phyaddr, phy_interface_t interface)
++ int phyaddr)
{
struct phy_device *phydev;
struct ofnode_phandle_args phandle_args;
}
id = vendor << 16 | device;
- phydev = phy_device_create(bus, phyaddr, id, false, interface);
- phydev = phy_device_create(bus, 0, id, false);
++ phydev = phy_device_create(bus, phyaddr, id, false);
if (phydev)
phydev->node = node;
#ifdef CONFIG_PHY_ETHERNET_ID
if (!phydev)
- phydev = phy_connect_phy_id(bus, dev, addr, interface);
- phydev = phy_connect_phy_id(bus, dev);
++ phydev = phy_connect_phy_id(bus, dev, addr);
#endif
#ifdef CONFIG_PHY_XILINX_GMII2RGMII
return 0;
}
- int phy_get_interface_by_name(const char *str)
- {
- int i;
-
- for (i = 0; i < PHY_INTERFACE_MODE_COUNT; i++) {
- if (!strcmp(str, phy_interface_strings[i]))
- return i;
- }
-
- return -1;
- }
-
+
+/**
+ * phy_modify - Convenience function for modifying a given PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @mask: bit mask of bits to clear
+ * @set: new value of bits set in mask to write to @regnum
+ */
+int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
+ u16 set)
+{
+ int ret;
+
+ ret = phy_read(phydev, devad, regnum);
+ if (ret < 0)
+ return ret;
+
+ return phy_write(phydev, devad, regnum, (ret & ~mask) | set);
+}
* @return: pointer to phy_device if a PHY is found,
* or NULL otherwise
*/
-struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev);
+struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev,
- int phyaddr, phy_interface_t interface);
++ int phyaddr);
static inline ofnode phy_get_ofnode(struct phy_device *phydev)
{
CONFIG_DM9000_DEBUG
CONFIG_DM9000_NO_SROM
CONFIG_DM9000_USE_16BIT
-CONFIG_DMA_COHERENT
-CONFIG_DMA_COHERENT_SIZE
-CONFIG_DP_DDR_CTRL
CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR
-CONFIG_DP_DDR_NUM_CTRLS
--CONFIG_DRIVER_DM9000
CONFIG_DSP_CLUSTER_START
CONFIG_DWC_AHSATA_BASE_ADDR
CONFIG_DWC_AHSATA_PORT_ID