zynqmp-mini-qspi.dtb \
zynqmp-sc-revB.dtb \
zynqmp-sc-revC.dtb \
+ zynqmp-sc-vek280-revA.dtbo \
+ zynqmp-sc-vek280-revB.dtbo \
+ zynqmp-sc-vhk158-revA.dtbo \
+ zynqmp-sc-vpk120-revB.dtbo \
+ zynqmp-sc-vpk180-revA.dtbo \
+ zynqmp-sc-vpk180-revB.dtbo \
+ zynqmp-sc-vn-p-b2197-00-revA.dtbo \
zynqmp-sm-k24-revA.dtb \
zynqmp-smk-k24-revA.dtb \
zynqmp-sm-k26-revA.dtb \
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VEK280 revA
+ *
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA",
+ "xlnx,zynqmp-vek280", "xlnx,zynqmp";
+
+ vc7_xin: vc7-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "", "", "SFP_MOD_ABS", "SFP_TX_DISABLE", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir35215_46: pmic@46 { /* IR35215 - u152 */
+ compatible = "infineon,ir35215";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: pmic@48 { /* IRPS5401 - u279 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38064_49: regulator@49 { /* IR38064 - u295 */
+ compatible = "infineon,ir38064";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38060_4e: regulator@4e { /* IR38060 - u282 */
+ compatible = "infineon,ir38060";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* alerts coming to u233 and SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <500>; /* r440 */
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <500>; /* r1702 */
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r382 */
+ };
+ vcc_ram: ina226@43 { /* u355 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r2417 */
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>; /* r1830 */
+ };
+ vcc_psfp: ina226@45 { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r2386 */
+ };
+ vcco_hdio: ina226@46 { /* u356 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>; /* r2392 */
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* alerts coming to u233 and SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>; /* r2384 */
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r2000 */
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1829 */
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r2397 */
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r2401 */
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <500>; /* r1384 */
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* r1994 */
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>; /* r2384 */
+ };
+ vcc1v1_lp4: ina226@49 { /* u306 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <500>; /* r2064 */
+ };
+ vadj_fmc: ina226@4a { /* u281 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>; /* r2031 */
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>; /* r2004 */
+ };
+ lpdmgtyavtt: ina226@4c { /* u309 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <5000>; /* r1229 */
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>; /* r1679 */
+ };
+ };
+ i2c@4 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ rc21008a_gtclk1: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* connector j374 */
+ /* rc21008a at 0x9 u299 */
+ vc7: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ };
+ fmcp1_iic: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* to j51c */
+ };
+ sfp: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* sfp+ connector J376 */
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VEK280 revB
+ *
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include "zynqmp-sc-vek280-revA.dtso"
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB",
+ "xlnx,zynqmp-vek280", "xlnx,zynqmp";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VHK158 revA
+ *
+ * (C) Copyright 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA",
+ "xlnx,zynqmp-vhk158", "xlnx,zynqmp";
+
+ vc7_xin: vc7-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "", "", "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38064_41: regulator@41 { /* IR38064 - u294 */
+ compatible = "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ irps5401_45: pmic5401@45 { /* IRPS5401 - u280 */
+ compatible = "infineon,irps5401";
+ reg = <0x45>; /* i2c addr 0x15 */
+ };
+ ir35221_46: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: regulator@48 { /* IRPS5401 - u279 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u295 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ ir38060_4a: regulator@4a { /* IR38060 - u259 */
+ compatible = "infineon,ir38164";
+ reg = <0x4a>; /* i2c addr 0x1a */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38060_4e: regulator@4e { /* IR38060 - u282 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <500>; /* R440 */
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <500>; /* R1702 */
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* R382 */
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <500>; /* R121 */
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>; /* R1830 */
+ };
+ vcc_psfp: ina226@45 { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* R1834 */
+ };
+ vcco_hbm: ina226@46 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <500>; /* R2056 */
+ };
+ vcc_hbm: ina226@47 { /* u307 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <500>; /* R2068 */
+ };
+ vccaux_hbm: ina226@48 { /* u308 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>; /* R2019 */
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>; /* R2060 */
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <500>; /* R2000 */
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <500>; /* R1829 */
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <500>; /* R1221 */
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <500>; /* R2015 */
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <500>; /* R1384 */
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <500>; /* R1994 */
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <500>; /* R1232 */
+ };
+ vcc1v2_rdimm: ina226@49 { /* u306 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <500>; /* R2064 */
+ };
+ vadj_fmc: ina226@4a { /* u281 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>; /* R2031 */
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <500>; /* R2004 */
+ };
+ lpdmgtyavtt: ina226@4c { /* u309 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <500>; /* R1229 */
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <500>; /* R1679 */
+ };
+ };
+ i2c@4 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ rc21008a_gtclk1: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ vc7_1: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-0";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* i2c@9 - U299 */
+ };
+ rc21008a_gtclk2: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ vc7_2: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-1";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* i2c@9 - U300 */
+ };
+ sync_8a34001: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* U219 - i2c address UNKNOWN */
+ };
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ ddr4_dimm0: i2c@0 { /* wired but NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ qsfp1_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J350 connector */
+ };
+ qsfp2_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* J351 connector */
+ };
+ qsfp3_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* J352 connector */
+ };
+ qsfp4_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* J353 connector */
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2 connectors */
+ };
+ ddr4_dimm1: i2c@7 { /* wired but NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2)
+ *
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ compatible = "xlnx,zynqmp-sc-vn-p-b2197-revA",
+ "xlnx,zynqmp-sc-vn-p-b2197", "xlnx,zynqmp";
+
+ aliases {
+ nvmem1 = &x_prc_eeprom;
+ };
+
+ ina226-u1700 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>;
+ };
+ ina226-u1732 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcc_lpd_ina 0>, <&vcc_lpd_ina 1>, <&vcc_lpd_ina 2>;
+ };
+ ina226-u1733 {
+ compatible = "iio-hwmon";
+ io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>;
+ };
+ ina226-u1736 {
+ compatible = "iio-hwmon";
+ io-channels = <&vccaux_lpd_ina 0>, <&vccaux_lpd_ina 1>, <&vccaux_lpd_ina 2>;
+ };
+ ina226-u1737 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>;
+ };
+ ina226-u1739 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>;
+ };
+ ina226-u1741 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>;
+ };
+ ina226-u1743 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>;
+ };
+ ina226-u1745 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_700_ina 0>, <&vcco_700_ina 1>, <&vcco_700_ina 2>;
+ };
+ ina226-u1747 {
+ compatible = "iio-hwmon";
+ io-channels = <&vcco_706_ina 0>, <&vcco_706_ina 1>, <&vcco_706_ina 2>;
+ };
+ ina226-u1750 {
+ compatible = "iio-hwmon";
+ io-channels = <>yp_avcc_ina 0>, <>yp_avcc_ina 1>, <>yp_avcc_ina 2>;
+ };
+ ina226-u1752 {
+ compatible = "iio-hwmon";
+ io-channels = <>yp_avtt_ina 0>, <>yp_avtt_ina 1>, <>yp_avtt_ina 2>;
+ };
+ ina226-u1754 {
+ compatible = "iio-hwmon";
+ io-channels = <>yp_avccaux_ina 0>, <>yp_avccaux_ina 1>, <>yp_avccaux_ina 2>;
+ };
+ ina226-u1756 {
+ compatible = "iio-hwmon";
+ io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>;
+ };
+ ina226-u1758 {
+ compatible = "iio-hwmon";
+ io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>;
+ };
+ ina226-u1760 {
+ compatible = "iio-hwmon";
+ io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>;
+ };
+
+ /* sc_vpk180_axi_iic_0_0: i2c@80050000 - UNUSED NOW */ /* SI5332 */
+
+ /* Connect to J212G pin G29/G30 - sysmon connector */
+ /* sc_vpk180_axi_iic_1_0: i2c@80060000 */ /* SYSMON */
+
+ /* FIXME Fan control via u1702 - max6643 and mux via J1703 - not SW controllable - via EMIO */
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* u97 eeprom at 0x54 described in sc-revB - WP protection via BOARD_EEPROM_WP - J1801 */
+ /* DC/SE eeprom at 0x52 */
+ x_prc_eeprom: eeprom@52 { /* u4 - DC card identification - possible WP */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ bootph-all;
+ };
+
+ x_prc_tca9534: gpio@22 { /* u5 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "xprc_sw_1", "xprc_sw_2", "xprc_sw_3", "xprc_sw_4",
+ "", "", "", "";
+ gtr-sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "xprc_sw_1";
+ };
+ gtr-sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "xprc_sw_1";
+ };
+ gtr-sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "xprc_sw_1";
+ };
+ gtr-sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "xprc_sw_1";
+ };
+ };
+
+ /* FMC eeproms at 0x50/0x51 */
+ /* via j3/j5 to 0x68 to u32/9FGV1006C
+
+ /* i2c_main_1 - u147 - j157 - disable translation, add 8 */
+ /* J1 - OE for u43@55 + 8 - 161,132813MHz - QSFP56G_0 */
+ qsfp56g_0_clk: clock-controller@5d {
+ compatible = "renesas,proxo-xp";
+ reg = <0x5d>;
+ #clock-cells = <0>;
+ clock-output-names = "qsfp56g_0_clk";
+ };
+
+ /* J2 - OE for u41@57 + 8 - 322,265625MHz - QSFP56G_1 */
+ qsfp56g_1_clk: clock-controller@5f {
+ compatible = "renesas,proxo-xp";
+ reg = <0x5f>;
+ #clock-cells = <0>;
+ clock-output-names = "qsfp56g_1_clk";
+ };
+
+ /* J81 - OE for u115@50 + 8 - 320MHz - LPDDR5_C0 */
+ lpddr5_c0_clk: clock-controller@58 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x58>;
+ #clock-cells = <0>;
+ clock-output-names = "lpddr5_c0_clk";
+ };
+
+ /* i2c_main_2 - u148 - j122 - disable translation, add 9 */
+ /* J112 - OE for u63@50 + 9 - 320MHz - LPDDR5_C2 */
+ lpddr5_c2_clk: clock-controller@59 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x59>;
+ #clock-cells = <0>;
+ clock-output-names = "lpddr5_c2_clk";
+ };
+
+ /* i2c_main_3 - u149 - j154 - disable translation, add 6 */
+ /* J78 - OE for u116@50 + 6 - 320MHz - DDR5_UDIMM */
+ ddr5_udimm_clk: clock-controller@56 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x56>;
+ #clock-cells = <0>;
+ clock-output-names = "ddr5_udimm_clk";
+ };
+
+ /* i2c_main_4 - u150 - j146 - disable translation, add 5 */
+ /* J107 - OE for u39@50 + 5 - 33,3333MHz - PS_REFCLK */
+ ps_refclk: clock-controller@55 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x55>;
+ #clock-cells = <0>;
+ clock-output-names = "ps_refclk";
+ };
+
+ /* i2c_main_5 - u1782 - j1798 - disable translation, add 7 */
+ /* J77 - OE for u1783@50 + 7 - 320MHz - DDR4 */
+ ddr4_clk: clock-controller@57 {
+ compatible = "renesas,proxo-xp";
+ reg = <0x57>;
+ #clock-cells = <0>;
+ clock-output-names = "ddr4_clk";
+ };
+
+ /* LTC4316 - not wired XORH/XORL - FIXME */
+ /* J3 gate - FIXME should be connected for SW handling */
+ /* i2c_main_1 bus */
+ i2c1_u32: clock-controller@68 {
+ compatible = "renesas,9fgv1006";
+ reg = <0x68>;
+ };
+
+ /* J71 - selection to LP_I2C_SCL_J or LP_I2C_PMC_SCL_J */
+ /* J70 - selection to LP_I2C_SDA_J or LP_I2C_PMC_SDA_J */
+ /* this should be SW controlable too */
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Via j11/j12 can also go to u17/IML3112 - 1:2 multiplexer - also accessed from Versal NET */
+ /* Connection DDR5_UDIMM - SPD can be from 0x50-0x57 */
+ /* FIXME gpio should handle SYSCTLR_PMBUS_ALERT and also INA226_PMBUS_ALERT */
+
+ /* ina226_pmbus - J55 - disable INA226_PMBUS */
+ vcc_ram_ina: power-monitor@40 { /* u1700 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x40>;
+ shunt-resistor = <1000>; /* R1996 */
+ };
+
+ vcc_lpd_ina: power-monitor@41 { /* u1732 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x41>;
+ shunt-resistor = <1000>; /* R2017 */
+ };
+
+ vccaux_ina: power-monitor@42 { /* u1733 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x42>;
+ shunt-resistor = <1000>; /* R2037 */
+ };
+
+ vccaux_lpd_ina: power-monitor@43 { /* u1736 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x43>;
+ shunt-resistor = <1000>; /* R2057 */
+ };
+
+ vcco_500_ina: power-monitor@44 { /* u1737 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x44>;
+ shunt-resistor = <1000>; /* R2069 */
+ };
+
+ vcco_501_ina: power-monitor@45 { /* u1739 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x45>;
+ shunt-resistor = <1000>; /* R2089 */
+ };
+
+ vcco_502_ina: power-monitor@46 { /* u1741 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x46>;
+ shunt-resistor = <1000>; /* R2108 */
+ };
+
+ vcco_503_ina: power-monitor@47 { /* u1743 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x47>;
+ shunt-resistor = <1000>; /* R2127 */
+ };
+
+ vcco_700_ina: power-monitor@48 { /* u1745 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x48>;
+ shunt-resistor = <1000>; /* R2154 */
+ };
+
+ vcco_706_ina: power-monitor@49 { /* u1747 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x49>;
+ shunt-resistor = <1000>; /* R2175 */
+ };
+
+ gtyp_avcc_ina: power-monitor@4a { /* u1750 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4a>;
+ shunt-resistor = <1000>; /* R2195 */
+ };
+
+ gtyp_avtt_ina: power-monitor@4b { /* u1752 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4b>;
+ shunt-resistor = <1000>; /* R2215 */
+ };
+
+ gtyp_avccaux_ina: power-monitor@4c { /* u1754 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4c>;
+ shunt-resistor = <5000>; /* R2235 */
+ };
+
+ gtm_avcc_ina: power-monitor@4d { /* u1756 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4d>;
+ shunt-resistor = <1000>; /* R2256 */
+ };
+
+ gtm_avtt_ina: power-monitor@4e { /* u1758 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4e>;
+ shunt-resistor = <1000>; /* R2276 */
+ };
+
+ gtm_avccaux_ina: power-monitor@4f { /* u1760 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ reg = <0x4f>;
+ shunt-resistor = <5000>; /* R2296 */
+ };
+
+ /* pmbus - J50 - disable main PMBUS - also going to j132 */
+ vcc_ram: regulator@a { /* u1730 */
+ compatible = "ti,tps544b25";
+ reg = <0xa>;
+ };
+
+ vcc_lpd: regulator@b { /* u1731 */
+ compatible = "ti,tps544b25";
+ reg = <0xb>;
+ };
+
+ vccaux: regulator@1a { /* u1734 */
+ compatible = "ti,tps544b25";
+ reg = <0x1a>;
+ };
+
+ vcco_503: regulator@12 { /* u1744 */
+ compatible = "ti,tps546b24a";
+ reg = <0x12>;
+ };
+
+ vcco_700: regulator@16 { /* u1746 */
+ compatible = "ti,tps544b25";
+ reg = <0x16>;
+ };
+
+ vcco_706: regulator@17 { /* u1748 */
+ compatible = "ti,tps544b25";
+ reg = <0x17>;
+ };
+
+ gtm_avcc: regulator@23 { /* u1755 */
+ compatible = "ti,tps544b25";
+ reg = <0x23>;
+ };
+
+ gtm_avtt: regulator@24 { /* u1757 */
+ compatible = "ti,tps544b25";
+ reg = <0x24>;
+ };
+
+ gtm_avccaux: regulator@25 { /* u1759 */
+ compatible = "ti,tps544b25";
+ reg = <0x25>;
+ };
+
+ util_1v8: regulator@15 { /* u1765 */
+ compatible = "ti,tps544b25";
+ reg = <0x15>;
+ };
+
+ ucd90320: power-sequencer@73 { /* u1768 */
+ compatible = "ti,ucd90320";
+ reg = <0x73>;
+ };
+
+ /* EXT_PMBUS main - J10 - disable extended PMBUS */
+ vccint: tps53681@60 { /* u1712 - J1770 reset jumper */
+ compatible = "ti,tps53681", "ti,tps53679";
+ reg = <0x60>;
+ /* vccint, vcc_cpm5n */
+ };
+
+ vcc_io_soc: tps53681@61 { /* u1721 - J1772 reset jumper */
+ compatible = "ti,tps53681", "ti,tps53679";
+ reg = <0x61>;
+ /* vcc_io_soc, vcc_fpd */
+ };
+
+ vccaux_lpd: regulator@d { /* u1735 */
+ compatible = "ti,tps544b25";
+ reg = <0xd>;
+ };
+
+ vcco_500: regulator@13 { /* u1738 */
+ compatible = "ti,tps546b24a";
+ reg = <0x13>;
+ };
+
+ vcco_501: regulator@10 { /* u1740 */
+ compatible = "ti,tps546b24a";
+ reg = <0x10>;
+ };
+
+ vcco_502: regulator@11 { /* u1742 */
+ compatible = "ti,tps546b24a";
+ reg = <0x11>;
+ };
+
+ gtyp_avcc: regulator@20 { /* u1749 */
+ compatible = "ti,tps544b25";
+ reg = <0x20>;
+ };
+
+ gtyp_avtt: regulator@21 { /* u1751 */
+ compatible = "ti,tps544b25";
+ reg = <0x21>;
+ };
+
+ gtyp_avccaux: regulator@22 { /* u1753 */
+ compatible = "ti,tps544b25";
+ reg = <0x22>;
+ };
+
+ lp5_vdd1_1v8: regulator@e { /* u1761 - FIXME no ina226 */
+ compatible = "ti,tps544b25";
+ reg = <0xe>;
+ };
+
+ lp5_vdd2_1v05: regulator@f { /* u1762 - FIXME no ina226 */
+ compatible = "ti,tps544b25";
+ reg = <0xf>;
+ };
+
+ lp5_vddq_0v5: regulator@14 { /* u1763 - FIXME no ina226 */
+ compatible = "ti,tps546b24a";
+ reg = <0x14>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VPK120 revB
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB",
+ "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "", "", "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38060_41: regulator@41 { /* IR38060 - u259 */
+ compatible = "infineon,ir38060", "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ ir38164_43: regulator@43 { /* IR38164 - u13 */
+ compatible = "infineon,ir38164";
+ reg = <0x43>; /* i2c addr 0x13 */
+ };
+ ir35221_46: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u189 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38164_4e: regulator@4e { /* IR38164 - u185 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ ir38164_4f: regulator@4f { /* IR38164 - u187 */
+ compatible = "infineon,ir38164";
+ reg = <0x4f>; /* i2c addr 0x1f */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ vcc_psfp: ina226@45 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v1_lp4: ina226@49 { /* u186 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <2000>;
+ };
+ vadj_fmc: ina226@4a { /* u184 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <2000>;
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ lpdmgtyavtt: ina226@4c { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <2000>;
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@4 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ i2c@5 { /* NC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ user_si570: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5f>;
+ temperature-stability = <50>;
+ factory-fout = <100000000>;
+ clock-frequency = <100000000>;
+ clock-output-names = "fmc_si570";
+ silabs,skip-recall;
+ };
+
+ };
+ /* 7 unused */
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ ref_clk_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ ref_clk: clock-generator@5d { /* u32 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ i2c@2 { /* NC - FIXME */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ lpddr4_si570_clk3_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ lpddr4_clk3: clock-generator@60 { /* u4 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk3";
+ silabs,skip-recall;
+ };
+ };
+ lpddr4_si570_clk2_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ lpddr4_clk2: clock-generator@60 { /* u3 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk2";
+ silabs,skip-recall;
+ };
+ };
+ lpddr4_si570_clk1_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ lpddr4_clk1: clock-generator@60 { /* u248 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk1";
+ silabs,skip-recall;
+ };
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2 connectors */
+ };
+ idt8a34001_i2c: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* Via J310 connector */
+ idt_8a34001: phc@5b {
+ compatible = "idt,8a34001"; /* u219B */
+ reg = <0x5b>; /* FIXME not in schematics */
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VPK180 revA
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA",
+ "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38060_41: regulator@41 { /* IR38060 - u259 */
+ compatible = "infineon,ir38060", "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ ir35221_45: pmic@45 { /* IR35221 - u291 */
+ compatible = "infineon,ir35221";
+ reg = <0x45>; /* i2c addr - 0x15 */
+ };
+ ir35221_46: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: pmic@48 { /* IRPS5401 - u295 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u189 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38164_4e: regulator@4e { /* IR38164 - u185 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ ir38164_4f: regulator@4f { /* IR38164 - u187 */
+ compatible = "infineon,ir38164";
+ reg = <0x4f>; /* i2c addr 0x1f */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>; /* r440 */
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r2174 */
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1214 */
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r2108 */
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>; /* r1830 */
+ };
+ vcc_psfp: ina226@45 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r2086 */
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>; /* r2109 */
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r1246 */
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1829 */
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r1221 */
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r1219 */
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>; /* r1384 */
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* r1825 */
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>; /* r1232 */
+ };
+ vcc1v1_lp4: ina226@49 { /* u186 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <2000>; /* r1367 */
+ };
+ vadj_fmc: ina226@4a { /* u184 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <2000>; /* r1350 */
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>; /* r2097 */
+ };
+ lpdmgtyavtt: ina226@4c { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <2000>; /* r1834 */
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>; /* r1679 */
+ };
+ };
+ /* 4 - 7 unused */
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c-mux-idle-disconnect;
+ /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ ref_clk_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ ref_clk: clock-generator@5d { /* u32 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <33333333>;
+ clock-frequency = <33333333>;
+ clock-output-names = "ref_clk";
+ silabs,skip-recall;
+ };
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ osfp_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J362 connector */
+ };
+ lpddr4_si570_clk3_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ lpddr4_clk3: clock-generator@60 { /* u4 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk3";
+ silabs,skip-recall;
+ };
+ /* alternative option DNP - u305 at 0x50 */
+ };
+ lpddr4_si570_clk2_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ lpddr4_clk2: clock-generator@60 { /* u3 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk2";
+ silabs,skip-recall;
+ };
+ /* alternative option DNP - u303 at 0x50 */
+ };
+ lpddr4_si570_clk1_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ lpddr4_clk1: clock-generator@60 { /* u248 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>;
+ temperature-stability = <50>;
+ factory-fout = <200000000>;
+ clock-frequency = <200000000>;
+ clock-output-names = "lpddr4_clk1";
+ silabs,skip-recall;
+ };
+ /* alternative option DNP - u301 at 0x50 */
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2/J355/J354/J359/J358 connectors */
+ };
+ idt8a34001_i2c: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* Via J310 connector */
+ idt_8a34001: phc@5b { /* u219B */
+ compatible = "idt,8a34001";
+ reg = <0x5b>;
+ };
+ };
+ };
+ i2c-mux@75 { /* u322 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c-mux-idle-disconnect;
+ /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ sfpdd1_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* J350 sfp-dd at 0x50 */
+ };
+ sfpdd2_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* J352 sfp-dd at 0x50 */
+ };
+ sfpdd3_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J385 sfp-dd at 0x50 */
+ };
+ sfpdd4_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* J387 sfp-dd at 0x50 */
+ };
+ rc21008a_gtclk1_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ vc7_1: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-0";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* u298 - rc21008a at 0x9 */
+ /* connector J370 */
+ };
+ rc21008a_gtclk2_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ vc7_2: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-1";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* u299 - rc21008a at 0x9 */
+ /* connector J371 */
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP VPK180 revA
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+/plugin/;
+
+
+&{/} {
+ compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB",
+ "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+
+ vc7_xin: vc7-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <50000000>;
+ };
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tca6416_u233: gpio@20 { /* u233 */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "QSFPDD1_MODSELL", "QSFPDD2_MODSELL", "QSFPDD3_MODSELL", "QSFPDD4_MODSELL", /* 0 - 3 */
+ "PMBUS2_INA226_ALERT", "QSFPDD5_MODSELL", "QSFPDD6_MODSELL", "", /* 4 - 7 */
+ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "UTIL_3V3_VRHOT_B", /* 10 - 13 */
+ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
+ };
+
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ pmbus_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J325 */
+ ir38060_41: regulator@41 { /* IR38060 - u259 */
+ compatible = "infineon,ir38060", "infineon,ir38064";
+ reg = <0x41>; /* i2c addr 0x11 */
+ };
+ ir35221_45: pmic@45 { /* IR35221 - u291 */
+ compatible = "infineon,ir35221";
+ reg = <0x45>; /* i2c addr - 0x15 */
+ };
+ ir35221_46: pmic@46 { /* IR35221 - u152 */
+ compatible = "infineon,ir35221";
+ reg = <0x46>; /* i2c addr - 0x16 */
+ };
+ irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
+ compatible = "infineon,irps5401";
+ reg = <0x47>; /* i2c addr 0x17 */
+ };
+ irps5401_48: pmic@48 { /* IRPS5401 - u295 */
+ compatible = "infineon,irps5401";
+ reg = <0x48>; /* i2c addr 0x18 */
+ };
+ ir38164_49: regulator@49 { /* IR38164 - u189 */
+ compatible = "infineon,ir38164";
+ reg = <0x49>; /* i2c addr 0x19 */
+ };
+ irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
+ compatible = "infineon,irps5401";
+ reg = <0x4c>; /* i2c addr 0x1c */
+ };
+ irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
+ compatible = "infineon,irps5401";
+ reg = <0x4d>; /* i2c addr 0x1d */
+ };
+ ir38164_4e: regulator@4e { /* IR38164 - u185 */
+ compatible = "infineon,ir38164";
+ reg = <0x4e>; /* i2c addr 0x1e */
+ };
+ ir38164_4f: regulator@4f { /* IR38164 - u187 */
+ compatible = "infineon,ir38164";
+ reg = <0x4f>; /* i2c addr 0x1f */
+ };
+ };
+ pmbus1_ina226_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts coming to SC */
+ vccint: ina226@40 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>; /* r440 */
+ };
+ vcc_soc: ina226@41 { /* u161 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r2174 */
+ };
+ vcc_pmc: ina226@42 { /* u163 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1214 */
+ };
+ vcc_ram: ina226@43 { /* u5 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r2108 */
+ };
+ vcc_pslp: ina226@44 { /* u165 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>; /* r1830 */
+ };
+ vcc_psfp: ina226@45 { /* u164 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r2086 */
+ };
+ };
+ i2c@2 { /* NC */ /* FIXME maybe remove */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ pmbus2_ina226_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u166 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>; /* r2109 */
+ };
+ vccaux_pmc: ina226@41 { /* u168 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>; /* r1246 */
+ };
+ mgtavcc: ina226@42 { /* u265 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>; /* r1829 */
+ };
+ vcc1v5: ina226@43 { /* u264 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>; /* r1221 */
+ };
+ vcco_mio: ina226@45 { /* u172 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>; /* r1219 */
+ };
+ mgtavtt: ina226@46 { /* u188 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>; /* r1384 */
+ };
+ vcco_502: ina226@47 { /* u174 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>; /* r1825 */
+ };
+ mgtvccaux: ina226@48 { /* u176 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>; /* r1232 */
+ };
+ vcc1v1_lp4: ina226@49 { /* u186 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <2000>; /* r1367 */
+ };
+ vadj_fmc: ina226@4a { /* u184 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <2000>; /* r1350 */
+ };
+ lpdmgtyavcc: ina226@4b { /* u177 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>; /* r2097 */
+ };
+ lpdmgtyavtt: ina226@4c { /* u260 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <2000>; /* r1834 */
+ };
+ lpdmgtyvccaux: ina226@4d { /* u234 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>; /* r1679 */
+ };
+ };
+ /* 4 - 7 unused */
+ };
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c-mux-idle-disconnect;
+ /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ fmcp1_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ osfp_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J362 connector */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* alternative option DNP - u305 at 0x50 */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* alternative option DNP - u303 at 0x50 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* alternative option DNP - u301 at 0x50 */
+ };
+ qsfpdd_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* J1/J2/J355/J354/J359/J358 connectors */
+ };
+ idt8a34001_i2c: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* Via J310 connector */
+ idt_8a34001: phc@5b { /* u219B */
+ compatible = "idt,8a34001";
+ reg = <0x5b>;
+ };
+ };
+ };
+ i2c-mux@75 { /* u322 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c-mux-idle-disconnect;
+ /* reset-gpios = <&PL_GPIO SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ sfpdd1_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* J350 sfp-dd at 0x50 */
+ };
+ sfpdd2_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* J352 sfp-dd at 0x50 */
+ };
+ sfpdd3_i2c: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* J385 sfp-dd at 0x50 */
+ };
+ sfpdd4_i2c: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* J387 sfp-dd at 0x50 */
+ };
+ rc21008a_gtclk1_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ vc7_1: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-0";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* u298 - rc21008a at 0x9 */
+ /* connector J370 */
+ };
+ rc21008a_gtclk2_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ vc7_2: clock-generator@9 {
+ compatible = "renesas,rc21008a";
+ clock-output-names = "rc21008a-1";
+ reg = <0x9>;
+ #clock-cells = <1>;
+ clocks = <&vc7_xin>;
+ clock-names = "xin";
+ };
+ /* u299 - rc21008a at 0x9 */
+ /* connector J371 */
+ };
+ };
+};
projects / u-boot.git / commitdiff
