ARM: zynq: Do not include full zynq-7000.dtsi to cse-nor configuration

There is no real need to include full DT when only some nodes are enough to
use. It will save some space.

Retested with FSBL for initial SoC setup. SPL didn't work.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
index 9710abadcf0246d9b83872aef698fb794cc76f17..4030851eb36dc335a53a7f23fae639862ce07c09 100644 (file)
--- a/arch/arm/dts/zynq-cse-nor.dts
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -5,7 +5,6 @@
  * Copyright (C) 2018 Xilinx, Inc.
  */
 /dts-v1/;
-#include "zynq-7000.dtsi"
 
 / {
        #address-cells = <1>;
@@ -33,27 +32,21 @@
        };
 
        amba: amba {
+               u-boot,dm-pre-reloc;
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
-               interrupt-parent = <&intc>;
                ranges;
 
-               intc: interrupt-controller@f8f01000 {
-                       compatible = "arm,cortex-a9-gic";
-                       #interrupt-cells = <3>;
-                       interrupt-controller;
-                       reg = <0xF8F01000 0x1000>,
-                             <0xF8F00100 0x100>;
-               };
-
                slcr: slcr@f8000000 {
+                       u-boot,dm-pre-reloc;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
                        reg = <0xF8000000 0x1000>;
                        ranges;
                        clkc: clkc@100 {
+                               u-boot,dm-pre-reloc;
                                #clock-cells = <1>;
                                compatible = "xlnx,ps7-clkc";
                                clock-output-names = "armpll", "ddrpll",