riscv: cpu: fu540: Add support for cpu fu540

Add SiFive fu540 cpu to support RISC-V arch

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fb5fe5affff1f3979279d030113872aee9755418..d9854f5283986ff031fc18b67ad6621032227d06 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -56,6 +56,7 @@ source "board/sifive/fu540/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
+source "arch/riscv/cpu/fu540/Kconfig"
 source "arch/riscv/cpu/generic/Kconfig"
 
 # architecture-specific options below

diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
new file mode 100644 (file)
index 0000000..e9302e8
--- /dev/null
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+config SIFIVE_FU540
+       bool
+       select ARCH_EARLY_INIT_R
+       imply CPU
+       imply CPU_RISCV
+       imply RISCV_TIMER
+       imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+       imply CMD_CPU
+       imply SPL_CPU_SUPPORT
+       imply SPL_OPENSBI
+       imply SPL_LOAD_FIT

diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
new file mode 100644 (file)
index 0000000..44700d9
--- /dev/null
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 SiFive, Inc
+# Pragnesh Patel <pragnesh.patel@sifive.com>
+
+obj-y += dram.o
+obj-y += cpu.o

diff --git a/arch/riscv/cpu/fu540/cpu.c b/arch/riscv/cpu/fu540/cpu.c
new file mode 100644 (file)
index 0000000..f13c189
--- /dev/null
+++ b/arch/riscv/cpu/fu540/cpu.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <irq_func.h>
+#include <asm/cache.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+       disable_interrupts();
+
+       cache_flush();
+
+       return 0;
+}

diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c
new file mode 100644 (file)
index 0000000..1dc77ef
--- /dev/null
+++ b/arch/riscv/cpu/fu540/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+       return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+       return fdtdec_setup_memory_banksize();
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_64BIT
+       /*
+        * Ensure that we run from first 4GB so that all
+        * addresses used by U-Boot are 32bit addresses.
+        *
+        * This in-turn ensures that 32bit DMA capable
+        * devices work fine because DMA mapping APIs will
+        * provide 32bit DMA addresses only.
+        */
+       if (gd->ram_top > SZ_4G)
+               return SZ_4G;
+#endif
+       return gd->ram_top;
+}

diff --git a/arch/riscv/include/asm/arch-fu540/clk.h b/arch/riscv/include/asm/arch-fu540/clk.h
new file mode 100644 (file)
index 0000000..d71ed43
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 SiFive Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#ifndef __CLK_SIFIVE_H
+#define __CLK_SIFIVE_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif

diff --git a/arch/riscv/include/asm/arch-fu540/gpio.h b/arch/riscv/include/asm/arch-fu540/gpio.h
new file mode 100644 (file)
index 0000000..0d16c59
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/gpio.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 SiFive, Inc.
+ */
+
+#ifndef _GPIO_SIFIVE_H
+#define _GPIO_SIFIVE_H
+
+#define GPIO_INPUT_VAL 0x00
+#define GPIO_INPUT_EN  0x04
+#define GPIO_OUTPUT_EN 0x08
+#define GPIO_OUTPUT_VAL        0x0C
+#define GPIO_RISE_IE   0x18
+#define GPIO_RISE_IP   0x1C
+#define GPIO_FALL_IE   0x20
+#define GPIO_FALL_IP   0x24
+#define GPIO_HIGH_IE   0x28
+#define GPIO_HIGH_IP   0x2C
+#define GPIO_LOW_IE    0x30
+#define GPIO_LOW_IP    0x34
+#define GPIO_OUTPUT_XOR        0x40
+
+#define NR_GPIOS       16
+
+enum gpio_state {
+       LOW,
+       HIGH
+};
+
+/* Details about a GPIO bank */
+struct sifive_gpio_platdata {
+       void *base;     /* address of registers in physical memory */
+};
+
+#define SIFIVE_GENERIC_GPIO_NR(port, index) \
+               (((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1)))
+
+#endif /* _GPIO_SIFIVE_H */

diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index d41c30522753341531bf32fc28e4bc2012f4fc1d..eb5ba3123d433b1d82a261790cab191125b7085f 100644 (file)
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
        default "sifive"
 
 config SYS_CPU
-       default "generic"
+       default "fu540"
 
 config SYS_CONFIG_NAME
        default "sifive-fu540"