pcm051: Support for revision 3

Phytec sells revision or version 3 of pcm051. It is labeled 1358.3 on
the board. The difference for u-boot is that is has other DDR3 RAM on it:
1 x MT41K256M16HA125E instead of 2 x MT41J256M8HX15E on revisions 1 and
2. Both configurations are 512 MiB.
Configure your u-boot build with pcm051_rev3 for the new RAM and
pcm051_rev1 for the old RAM configuration. Board revision 2 has to use
pcm051_rev1 also.

Signed-off-by: Lars Poeschel <poeschel@lemonage.de>

diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index dafb1eb8e633fdbf3443a2038ca18160f65407a3..bd1bb70939d3ed65d9209e7affdaf2f5406da27c 100644 (file)
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -49,6 +49,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
        return &dpll_ddr;
 }
 
+#ifdef CONFIG_REV1
 static const struct ddr_data ddr3_data = {
        .datardsratio0 = MT41J256M8HX15E_RD_DQS,
        .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
@@ -82,6 +83,52 @@ static struct emif_regs ddr3_emif_reg_data = {
                                PHY_EN_DYN_PWRDN,
 };
 
+void sdram_init(void)
+{
+       config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
+                  &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#else
+static const struct ddr_data ddr3_data = {
+       .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+       .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+       .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+       .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+       .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+       .cmd0csratio = MT41K256M16HA125E_RATIO,
+       .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
+       .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+       .cmd1csratio = MT41K256M16HA125E_RATIO,
+       .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
+       .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+       .cmd2csratio = MT41K256M16HA125E_RATIO,
+       .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
+       .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+       .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+       .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+       .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+       .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+       .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+       .zq_config = MT41K256M16HA125E_ZQ_CFG,
+       .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
+                               PHY_EN_DYN_PWRDN,
+};
+
+void sdram_init(void)
+{
+       config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data,
+                  &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif
+
 void set_uart_mux_conf(void)
 {
        enable_uart0_pin_mux();
@@ -95,12 +142,6 @@ void set_mux_conf_regs(void)
 
        enable_board_pin_mux();
 }
-
-void sdram_init(void)
-{
-       config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
-                       &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
 #endif
 
 /*

diff --git a/boards.cfg b/boards.cfg
index cff9aab9b1960b3976d1a9d683a61eb471213e2c..70755bb16fce7ca26d102bf37fd3794fa210c6c2 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -246,7 +246,8 @@ Active  arm         armv7          -           armltd          vexpress
 Active  arm         armv7          -           armltd          vexpress            vexpress_ca9x4                       -                                                                                                                                 Matt Waddel <matt.waddel@linaro.org>
 Active  arm         armv7          am33xx      compulab        cm_t335             cm_t335                              cm_t335                                                                                                                           Igor Grinberg <grinberg@compulab.co.il>
 Active  arm         armv7          am33xx      isee            igep0033            am335x_igep0033                      -                                                                                                                                 Enric Balletbo i Serra <eballetbo@iseebcn.com>
-Active  arm         armv7          am33xx      phytec          pcm051              pcm051                               pcm051                                                                                                                            Lars Poeschel <poeschel@lemonage.de>
+Active  arm         armv7          am33xx      phytec          pcm051              pcm051_rev1                          pcm051:REV1                                                                                                                       Lars Poeschel <poeschel@lemonage.de>
+Active  arm         armv7          am33xx      phytec          pcm051              pcm051_rev3                          pcm051:REV3                                                                                                                       Lars Poeschel <poeschel@lemonage.de>
 Active  arm         armv7          am33xx      siemens         dxr2                dxr2                                 -                                                                                                                                 Roger Meier <r.meier@siemens.com>
 Active  arm         armv7          am33xx      siemens         pxm2                pxm2                                 -                                                                                                                                 Roger Meier <r.meier@siemens.com>
 Active  arm         armv7          am33xx      siemens         rut                 rut                                  -                                                                                                                                 Roger Meier <r.meier@siemens.com>