rockchip: rk3399: Add option to print on UART3.

The RK3399 SPL does not use a pinctrl driver to setup the UART pins.
Instead it works based on config macros, which set the base address
of the actual UART block.

Currently the RK3399 SPL support UART0 and UART2.
This patch adds UART3 in the same way as UART0.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index a7ccd4f3ed2c6177045883ba9a69bc638f0209a4..e1f9f8b8efe8e7042427e09b618319541e51f179 100644 (file)
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -80,6 +80,14 @@ void board_debug_uart_init(void)
        rk_clrsetreg(&grf->gpio2c_iomux,
                     GRF_GPIO2C1_SEL_MASK,
                     GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
+       /* Enable early UART3 on the RK3399 */
+       rk_clrsetreg(&grf->gpio3b_iomux,
+                    GRF_GPIO3B6_SEL_MASK,
+                    GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
+       rk_clrsetreg(&grf->gpio3b_iomux,
+                    GRF_GPIO3B7_SEL_MASK,
+                    GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
 #else
 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
        rk_setreg(&grf->io_vsel, 1 << 0);